GB1363431A - Method of electrically connecting a semiconductor chip to a sub strate - Google Patents
Method of electrically connecting a semiconductor chip to a sub strateInfo
- Publication number
- GB1363431A GB1363431A GB5572170A GB5572170A GB1363431A GB 1363431 A GB1363431 A GB 1363431A GB 5572170 A GB5572170 A GB 5572170A GB 5572170 A GB5572170 A GB 5572170A GB 1363431 A GB1363431 A GB 1363431A
- Authority
- GB
- United Kingdom
- Prior art keywords
- portions
- solder
- neck
- terminal
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 229910000679 solder Inorganic materials 0.000 abstract 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 239000010949 copper Substances 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
1363431 Soldering JOSEPH LUCAS (INDUSTRIES) Ltd 15 Nov 1971 [24 Nov 1970 25 Feb 1971] 55721/70 and 5484/71 Heading B3R [Also in Division H1] In connecting a semi-conductor chip having solderable projections to a substrate, a plurality of conductive areas 11 are provided on the substrate, each area including a terminal portion 12 and a narrower neck portion 13, a dam 14 formed of a material which is not wetted by solder is provided on each neck portion 13, molten solder is provided on the terminal portions, the dimensions of the neck portions being such that flow of solder away from the terminal portions is resisted and the arrangement being such that a raised solder land is formed on each terminal portion, the projections on the chip are engaged with the lands and the assembly is heated to fuse the solder. The length of each portion 13 is not less than 1À5 times the length of its portion 12 and its width not more than half the width of its portion 12. The portions 12 although shown square may be circular and the neck portions 13 may be other than rectangular. The dams may be of glass. When the molten solder 14 is applied only a very thin coating is formed on the neck portions with a large amount on the portions 12 and remainder of area 11. The chip is inverted so that solder pads or copper balls soldered thereto are presented to the lands which when the assembly is heated form the soldered connections. More than one neck portion may be provided to join a terminal portion to the rest of the conductive area.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5572170A GB1363431A (en) | 1970-11-24 | 1970-11-24 | Method of electrically connecting a semiconductor chip to a sub strate |
AU35885/71A AU3588571A (en) | 1970-11-24 | 1971-11-18 | A method of electrically connecting a semiconductor chip toa substrate |
IT5424171A IT945066B (en) | 1970-11-24 | 1971-11-22 | METHOD OF CONNECTING A SEMICONDUCTOR WITH A SUBSTRATE AND RESULTING CIRCUIT |
DE19712157956 DE2157956A1 (en) | 1970-11-24 | 1971-11-23 | Method for electrically connecting a semiconductor chip to a substrate |
FR7142146A FR2115393A1 (en) | 1970-11-24 | 1971-11-24 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5572170A GB1363431A (en) | 1970-11-24 | 1970-11-24 | Method of electrically connecting a semiconductor chip to a sub strate |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1363431A true GB1363431A (en) | 1974-08-14 |
Family
ID=10474695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5572170A Expired GB1363431A (en) | 1970-11-24 | 1970-11-24 | Method of electrically connecting a semiconductor chip to a sub strate |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1363431A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4536786A (en) * | 1976-08-23 | 1985-08-20 | Sharp Kabushiki Kaisha | Lead electrode connection in a semiconductor device |
-
1970
- 1970-11-24 GB GB5572170A patent/GB1363431A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4536786A (en) * | 1976-08-23 | 1985-08-20 | Sharp Kabushiki Kaisha | Lead electrode connection in a semiconductor device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |