GB1339293A - Method of manufacturing a planar semiconductor device - Google Patents

Method of manufacturing a planar semiconductor device

Info

Publication number
GB1339293A
GB1339293A GB4239471A GB4239471A GB1339293A GB 1339293 A GB1339293 A GB 1339293A GB 4239471 A GB4239471 A GB 4239471A GB 4239471 A GB4239471 A GB 4239471A GB 1339293 A GB1339293 A GB 1339293A
Authority
GB
United Kingdom
Prior art keywords
layer
silicon nitride
semi
sept
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4239471A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Publication of GB1339293A publication Critical patent/GB1339293A/en
Expired legal-status Critical Current

Links

Classifications

    • H10P14/69433—
    • H10P14/6334—
    • H10P14/6504—
    • H10P14/6512—
    • H10P14/662—
    • H10P14/6682—
    • H10P14/69215—
    • H10W74/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/113—Nitrides of boron or aluminum or gallium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

Landscapes

  • Formation Of Insulating Films (AREA)
GB4239471A 1970-09-30 1971-09-10 Method of manufacturing a planar semiconductor device Expired GB1339293A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702047998 DE2047998A1 (de) 1970-09-30 1970-09-30 Verfahren zum Herstellen einer Planaranordnung

Publications (1)

Publication Number Publication Date
GB1339293A true GB1339293A (en) 1973-11-28

Family

ID=5783765

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4239471A Expired GB1339293A (en) 1970-09-30 1971-09-10 Method of manufacturing a planar semiconductor device

Country Status (5)

Country Link
US (1) US3798062A (enExample)
AU (1) AU454548B2 (enExample)
DE (1) DE2047998A1 (enExample)
FR (1) FR2108122B1 (enExample)
GB (1) GB1339293A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5635024B2 (enExample) * 1973-12-14 1981-08-14
JPS5922381B2 (ja) * 1975-12-03 1984-05-26 株式会社東芝 ハンドウタイソシノ セイゾウホウホウ
DE2836911C2 (de) * 1978-08-23 1986-11-06 Siemens AG, 1000 Berlin und 8000 München Passivierungsschicht für Halbleiterbauelemente
FR3125770B1 (fr) 2021-07-27 2023-10-06 Psa Automobiles Sa Procédé d’ouverture d’un véhicule et clef mains libres associée.

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3281915A (en) * 1963-04-02 1966-11-01 Rca Corp Method of fabricating a semiconductor device
US3503813A (en) * 1965-12-15 1970-03-31 Hitachi Ltd Method of making a semiconductor device
US3438873A (en) * 1966-05-11 1969-04-15 Bell Telephone Labor Inc Anodic treatment to alter solubility of dielectric films
US3455020A (en) * 1966-10-13 1969-07-15 Rca Corp Method of fabricating insulated-gate field-effect devices
NL162250C (nl) * 1967-11-21 1980-04-15 Philips Nv Halfgeleiderinrichting met een halfgeleiderlichaam, waarvan aan een hoofdoppervlak het halfgeleideroppervlak plaatselijk met een oxydelaag is bedekt, en werkwijze voor het vervaardigen van planaire halfgeleider- inrichtingen.
US3607697A (en) * 1968-04-18 1971-09-21 Sprague Electric Co Sputtering process for making a film of silica and silicon nitride
US3658678A (en) * 1969-11-26 1972-04-25 Ibm Glass-annealing process for encapsulating and stabilizing fet devices

Also Published As

Publication number Publication date
DE2047998A1 (de) 1972-04-06
AU3343071A (en) 1973-03-22
US3798062A (en) 1974-03-19
FR2108122B1 (enExample) 1974-06-07
FR2108122A1 (enExample) 1972-05-12
AU454548B2 (en) 1974-10-31

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees