GB1200078A - A method of manufacturing a semiconductor device and a device obtained by this method - Google Patents

A method of manufacturing a semiconductor device and a device obtained by this method

Info

Publication number
GB1200078A
GB1200078A GB4016967A GB4016967A GB1200078A GB 1200078 A GB1200078 A GB 1200078A GB 4016967 A GB4016967 A GB 4016967A GB 4016967 A GB4016967 A GB 4016967A GB 1200078 A GB1200078 A GB 1200078A
Authority
GB
United Kingdom
Prior art keywords
layer
oxide
semi
substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4016967A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1200078A publication Critical patent/GB1200078A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

1,200,078. Semi-conductor devices. HITACHI Ltd. 1 Sept., 1967 [12 Sept., 1966], No. 40169/67. Heading H1K. A semi-conductor substrate 1 coated with a passivating layer 4 (e.g. of SiO 2 ) is further coated with a layer 5 comprising an oxide of phosphorus, boron or lead by exposing the layer 4 to a material containing one of these elements and simultaneously heating it in an oxidizing atmosphere and is immediately thereafter coated with a further protective layer 6 (e.g. of SiO 2 ), this final coating step being performed without permitting the oxide layer 5 to be exposed to a moisture-containing atmosphere. In the preferred embodiment the surface of a diffused planar-type silicon NPN transistor is cleaned of any oxide masking layer and is thereafter provided with an oxide passivation layer 4 by the decomposition by heating in a reaction tube under reduced pressure of a gaseous organic silane (e.g. tetraethoxysilane). The surface of the oxide layer 4 is vitrified to produce layer 5 by the passage of gaseous POCI 3 in oxygen at an elevated temperature, the glass layer thus formed then being protected by a repetition of the process which results in the deposition of oxide film 4, these further two processes being carried out without interruption in the same reaction tube. As a result, any free phosphorus pentoxide remaining on the surface of the layer 5 cannot react with moisture in the atmosphere to produce a gel which degrades the properties of the semi-conductor device. The function of the vitreous layer 5 is to improve the sealing properties of the passivating layer 4 and to reduce migration of any metallic ions therein. Fig. 4 (not shown) shows the completed devices wherein holes are etched through the layers 4, 5 and 6 and aluminium contacts plated therethrough on to the base and emitter electrode areas. It is stated that in the case of a silicon substrate the layer 4 may be formed either by deposition or by oxidation of the substrate, that the substrate may be of germanium or an intermetallic semi-conductor compound and that the invention is applicable to mesa transistors, to diodes and integrated circuits. The layer 6 may be formed of Si 3 N 4 . Reference has been directed by the Comptroller to Specification 1,049,017.
GB4016967A 1966-09-12 1967-09-01 A method of manufacturing a semiconductor device and a device obtained by this method Expired GB1200078A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5983566 1966-09-12

Publications (1)

Publication Number Publication Date
GB1200078A true GB1200078A (en) 1970-07-29

Family

ID=13124664

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4016967A Expired GB1200078A (en) 1966-09-12 1967-09-01 A method of manufacturing a semiconductor device and a device obtained by this method

Country Status (2)

Country Link
DE (1) DE1589900B2 (en)
GB (1) GB1200078A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2658304C2 (en) * 1975-12-24 1984-12-20 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa Semiconductor device
US4161743A (en) * 1977-03-28 1979-07-17 Tokyo Shibaura Electric Co., Ltd. Semiconductor device with silicon carbide-glass-silicon carbide passivating overcoat
DE2713647C2 (en) * 1977-03-28 1984-11-29 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa A semiconductor device composed of a semiconductor substrate and a surface protective film

Also Published As

Publication number Publication date
DE1589900B2 (en) 1972-09-14
DE1589900A1 (en) 1970-08-13

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees