GB1177320A - Improvements in or relating to the Production of Planar Semiconductor Components - Google Patents

Improvements in or relating to the Production of Planar Semiconductor Components

Info

Publication number
GB1177320A
GB1177320A GB6054668A GB6054668A GB1177320A GB 1177320 A GB1177320 A GB 1177320A GB 6054668 A GB6054668 A GB 6054668A GB 6054668 A GB6054668 A GB 6054668A GB 1177320 A GB1177320 A GB 1177320A
Authority
GB
United Kingdom
Prior art keywords
boron
diffusion
glass layer
layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB6054668A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19671614691 external-priority patent/DE1614691C3/en
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1177320A publication Critical patent/GB1177320A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)

Abstract

1,177,320. Semi-conductor devices. SIEMENS A.G. 20 Dec., 1968 [21 Dec., 1967], No. 60546/68. Heading H1K. A boron-oxide glass layer, produced during the diffusion of boron into a silicon wafer by a planar process, is heat treated in a moist atmosphere at a temperature of 300‹ to 900‹ C. to make it easier to etch and the treated glass layer is then completely or partially etched away. The glass layer may be covered with an oxide layer to prevent out diffusion of boron during the heat treatment. A diode, Figs. 1 and 2 (not shown), is produced by oxidizing the surface of an N-type silicon wafer, etching a window and diffusing-in boron to produce a P-type region. The boronoxide glass layer which forms during the diffusion is covered with a silicon dioxide layer by pyrolysis of tetraethoxysilane and the wafer is then heated in a stream of moist nitrogen. The surface is photo-resist masked and etched with hydrofluoric acid buffered with ammonium fluoride to expose areas of the diffused region and the substrate. A metal is then deposited in the windows to form electrodes which may be alloyed to the wafer. A PNP planar transistor, Fig. 3 (not shown), is produced by forming an N-type base layer at the upper face of a P-type silicon wafer by diffusion, oxidizing the surface, forming a window, and diffusing-in boron to produce a P-type emitter region. A layer of silicon dioxide is deposited over the boron-oxide glass layer formed during the diffusion, and the wafer is heated in a moist atmosphere. The surface is photo-masked and etched to expose part of the base region into which phosphorus is diffused to produce an N+ type base contact region. The high temperature phosphorus diffusion step reduces the etchability of the glass layer so that a second heat treatment in a moist atmosphere is necessary before masking and etching away the oxide and glass over the emitter region. Metal contacts are deposited on the exposed areas of the emitter and base regions and the collector contact is applied to the lower face of the body. Argon or oxygen may be used instead of nitrogen in the moist atmosphere.
GB6054668A 1967-12-21 1968-12-20 Improvements in or relating to the Production of Planar Semiconductor Components Expired GB1177320A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19671614691 DE1614691C3 (en) 1967-12-21 1967-12-21 Method for manufacturing semiconductor components
DE1967S0113442 DE1614691B2 (en) 1967-12-21 1967-12-21 Method for manufacturing semiconductor components

Publications (1)

Publication Number Publication Date
GB1177320A true GB1177320A (en) 1970-01-07

Family

ID=25753711

Family Applications (1)

Application Number Title Priority Date Filing Date
GB6054668A Expired GB1177320A (en) 1967-12-21 1968-12-20 Improvements in or relating to the Production of Planar Semiconductor Components

Country Status (4)

Country Link
DE (1) DE1614691B2 (en)
FR (1) FR1597835A (en)
GB (1) GB1177320A (en)
NL (1) NL6816421A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3837936A (en) * 1971-11-20 1974-09-24 Itt Planar diffusion method
US3850687A (en) * 1971-05-26 1974-11-26 Rca Corp Method of densifying silicate glasses
US4234361A (en) * 1979-07-05 1980-11-18 Wisconsin Alumni Research Foundation Process for producing an electrostatically deformable thin silicon membranes utilizing a two-stage diffusion step to form an etchant resistant layer
CN113113324A (en) * 2021-04-07 2021-07-13 捷捷半导体有限公司 Passivation layer manufacturing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2548289C2 (en) * 1975-10-29 1985-03-28 Telefunken electronic GmbH, 7100 Heilbronn Method for manufacturing a semiconductor component
FR2450505A1 (en) * 1979-03-02 1980-09-26 Thomson Csf SEMICONDUCTOR DEVICE COMPRISING A DIFFUSED GUARD RING AND MANUFACTURING METHOD THEREOF

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3850687A (en) * 1971-05-26 1974-11-26 Rca Corp Method of densifying silicate glasses
US3837936A (en) * 1971-11-20 1974-09-24 Itt Planar diffusion method
US4234361A (en) * 1979-07-05 1980-11-18 Wisconsin Alumni Research Foundation Process for producing an electrostatically deformable thin silicon membranes utilizing a two-stage diffusion step to form an etchant resistant layer
CN113113324A (en) * 2021-04-07 2021-07-13 捷捷半导体有限公司 Passivation layer manufacturing method
CN113113324B (en) * 2021-04-07 2024-02-06 捷捷半导体有限公司 Passivation layer manufacturing method

Also Published As

Publication number Publication date
DE1614691A1 (en) 1970-05-21
NL6816421A (en) 1969-06-24
FR1597835A (en) 1970-06-29
DE1614691B2 (en) 1975-12-04

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