GB1317053A - Search-minimized optimum processor - Google Patents

Search-minimized optimum processor

Info

Publication number
GB1317053A
GB1317053A GB2836370A GB2836370A GB1317053A GB 1317053 A GB1317053 A GB 1317053A GB 2836370 A GB2836370 A GB 2836370A GB 2836370 A GB2836370 A GB 2836370A GB 1317053 A GB1317053 A GB 1317053A
Authority
GB
United Kingdom
Prior art keywords
signals
processor
training
input
key
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2836370A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of GB1317053A publication Critical patent/GB1317053A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90Details of database functions independent of the retrieved data types
    • G06F16/901Indexing; Data structures therefor; Storage structures
    • G06F16/9027Trees

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Feedback Control In General (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

1317053 Trainable processors TEXAS INSTRUMENTS Inc 11 June 1970 [30 June 1969] 28363/70 Heading G4R In a trainable processor, similar to that described in Specification 1,264,387, training functions developed in the course of training are stored in a random access memory. For each set of input signals representing a training function key signals are generated to designate node locations defining a branch of a tree storage array. The key signals and training function are stored in the tree array in the random access memory. This arrangement reduces the number of storage locations required since a storage location is assigned as needed for each training function, whereas in the prior processor a location is provided uniquely for each of the possible combinations of all the quantization levels of the signals used in training. During training the processor is fed with a succession of sets of input signals u i and a corresponding series of signals representing the desired response z i of the processor to the signals u i . The signals are quantized and used to develop key signals which address locations in the memory. Quantized signals representing the output x i-1 of the processor in response to prior training signals are also used in the development of the key signals. The selected locations' contents are adjusted in accord with z i and u i . The branch in the tree storage is defined by the key signal, and this signal is compared with keys representing previously defined branches, if any. If such a path has previously been defined the content of the last storage location in the path is adjusted to correspond to the present input signal set. The adjustment to the content takes the form of adding the value of the desired response z i to the current content to provide a result which replaces the current content. The number of times that the location has been adjusted is accumulated, and the processor output signal x i is determined by dividing the adjusted content by this number. If no corresponding path has been previously defined the key signal defines a new path in the tree. During execution, the processor provides an output signal x i in response to an input u i , x i being obtained from the tree storage. If the processor encounters an untrained input it replaces this input by the value of the previous output.
GB2836370A 1969-06-30 1970-06-11 Search-minimized optimum processor Expired GB1317053A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83742569A 1969-06-30 1969-06-30

Publications (1)

Publication Number Publication Date
GB1317053A true GB1317053A (en) 1973-05-16

Family

ID=25274410

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2836370A Expired GB1317053A (en) 1969-06-30 1970-06-11 Search-minimized optimum processor

Country Status (5)

Country Link
CA (1) CA929273A (en)
DE (1) DE2032248A1 (en)
FR (1) FR2051456A5 (en)
GB (1) GB1317053A (en)
NL (1) NL7009361A (en)

Also Published As

Publication number Publication date
NL7009361A (en) 1971-01-04
DE2032248A1 (en) 1971-12-02
CA929273A (en) 1973-06-26
FR2051456A5 (en) 1971-04-02

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees