GB1272423A - Electric system - Google Patents

Abstract

1,272,423. D/A converter. INDUCTOSYN Ltd. 1 May, 1969 [14 May, 1968; 24 March, 1969], No. 58273/69. Divided out of 1,272,422. Heading G4H. By continually cycling two counters each having a capacity M by clock pulses of frequency Mf and appropriately combining their various outputs, two pulse trains S and C each of frequency f are produced, the durations of the pulses in the two pulse trains being such that the first harmonics contained within each pulse train are proportional to the sine and cosine respectively of the constant count difference between the two counters. As described each counter has a capacity of M = 20, the count difference is d which can have any even value from 0 to 20, and the durations of the pulses in the two pulse trains S and C, and their first harmonics are as follows: where 2#w = f. This result is achieved by two counters 11, 12, Fig. 1, driven by interleaved clock pulses of frequency Mf from NAND gates 390 and 390<SP>1</SP> respectively, gates 394 and 395 which combine appropriate outputs from the counters, and inverting amplifiers 398, 396 respectively, to produce pulse trains S and C, referenced " sin " and " cos " in the drawing. The output from gate 394 passes via an inverting network 397, 399, 400, 401, 402, controlled by a sign stage 314. Normally the output from the sign stage is high ( = " 1 ") and no inversion takes place, but when the output is low inversion is performed. The required count difference between the counters is established by resetting them by signals from gates 388 at appropriate times. The reset state, and the subsequent 19 states for each counter are as follows: from which it will be seen that stages B, C, D, and 387 function as a biquinary counter from 0 to 9, and that stage 386 takes the capacity up to 20. Stage A performs no active counting function, but merely serves to produce an output signal in phase-quadrature with that from stage 386. The outputs from these last two stages from both counters are combined in the manner shown. As described the system forms a part of the displacement measuring sytsem described in application (Serial No. 1,272,422) from which the present application is divided. In that application an interval counter of capacity 2000 stores a number n and a reference counter, also of capacity 2000, is constantly cycled by clock pulses of frequency 4 Mc/s. The output of these two counters are compared, mainly by circuits not shown and partly by the circuit in the small dotted box at the left hand side of Fig. 1, to produce signals +TU when both the tens and units denominations agree, +H when the hundreds denominations agree, and +Th when the thousands denominations agree. The nines complement of the internal counter is also compared with the reference counter to produce signals -TU, -H, and -TH respectively. When all + TU, + H and + TL are ones, complete agreement between the interval counter and the reference counter exists, and as a result, via gates 382, 366, 392 and 388, counter 11 is reset. This occurs at time n within a cycle of the reference counter and hence counter 11 is referred to as the +n counter. Similarly when the nines complement of the internal counter agrees with the reference count, counter 12 is reset, via gates 382<SP>1</SP>, 366<SP>1</SP>, 392<SP>1</SP>, and 388<SP>1</SP>, at time -(n+1). Hence counter 12 is referred to as the -n counter. Thus, with reference to the zero of the reference counter, third line from bottom, Fig. 3, counter 11 is reset n clock pulses later, and counter 12, (n+1) clock pulses earlier. In Fig. 3, n = 100 and the bleep 110 indicates when counter 11 is reset. Thus in terms of the count in the interval counter, counters 11 and 12 are reset at times n and -(n+1). Subsequent stepping pulses to counters 11 and 12, via gates 390 and 390<SP>1</SP>, occur at intervals of every 100 clock pulses when + TU = 1 and -TU = 1, respectively, except that the first stepping pulse to each counter after its reset may occur after either 100 or 101 clock pulses depending upon a control signal U/D N . If U/D N = 1, counter 11 receives its pulses via gates 383 and 384 and trigger 385, and the first occurs 101 clock pulses after reset while counter 12 receives its stepping pulses via gate 391<SP>1</SP> and the first occurs after 100 clock pulses. Thus the effective count difference established when U/D N = 1 is 2(n+1). When U/D N =0 gate 391, and gates 383<SP>1</SP>, 384<SP>1</SP> and trigger 385<SP>1</SP> are operative and the resulting effective count difference is 2n. Thus a count difference of 2(n+1) or 2n is established and counters 11 and 12 are stepped at a frequency of 40 kc/s. (the clock frequency being 4 Mc/s.). Since, as stated above M=20, the sin and cos output signals occur at a frequency of 2 kc/s. (=f). Also, 100d equals the integral part of the quotient of either 2(n+1) or 2n and 100. With a value of 100 for n, and when U/D N = 1, Fig. 3 shows the states of various stages of the counters, and the output pulses sin and cos. It will be noticed that the output pulses are centred around a count of n of the reference counter, so that although only the top digits of n determine the durations of the sin and cos pulses (since counters 11 and 12 are stepped by ŒTU signals) all four digits determine their phasing.