DE1924426C3 - Position measuring system - Google Patents

Description

The invention relates to a digitally operating position measuring system comprising a position measuring device of two measuring parts which are movable relative to one another, the first of which is attached to a first Machine part and the second is arranged on a second machine part, the second measuring part has several equidistant zero positions, and the system an internal counter, the digital content of which is a coordinate of the first measuring part between two zero positions of the second measuring part comprises an external counter and a display device, which, controlled by the external counter, displays the content of the external counter, and also a converter, which converts the digital content of the internal counter into analog signals for the position measuring device for generating an error signal as a function of the mutual adjustment of the two measuring parts and depending on the analog signals, and an internal logic control device are provided, which converts the error signal into digital pulses.

A digital sine-cosine generator as described in connection with FIG. 6 of the present invention is described and required for the operation of the position measuring device is in its details shown in German patent applications P 17 62 408.7 and P 19 56 881.1.

The position measuring system according to the present invention can be used in a simple manner Measuring devices and machine tools, for example horizontal and vertical boring mills, Jig boring machines, milling machines, grinding machines and lathes. The moving machine part

5 6

can be seen here by hand or by other adjustment, which are used for digital measurement and display of the means, such as a motor for measuring the position of a moving machine part relative to the dimensions of a fixed machine part arranged on the machine. During the neten workpiece can be positioned. normal working method is the way or the ver

When a workpiece is placed on the machine 5 position is saved.

is and is attached, the zero position of the factory is correct

Piece from which the workpiece to be measured moving machine part is relative to a reference, mostly does not coincide with the zero position of the position-zero position of one on the other machine part Measuring device. Although this difference or yer- attached workpiece appears. Here is a Settlement can be low, for example in the io measuring device with a large number of the same The order of magnitude of a few millimeters affects the spaced measuring cycles used. One this offset in the case of precise measurements as the bc reference position in these cycles is referred to as sin 0, significant error size. If this zero position The reference position of the workpiece is by an amount 1 difference, however, is used to offset the movable from one of these sin-O positions. The content Machine part in the correct relation to the zero start position 15 of an internal counter, which is from the measuring device to set the position measuring device, which is controlled, represents the position of the movable part subsequent measurements must be accurate. the measuring device between two neighboring ones

A sin-0 position that can be used well for position measuring systems. An outer counter and a Lagenmeßvorrichtung is for example in German display device show the instantaneous and U.S. Patent 1,104,601. 10 actual position of the moving part with respect to

In this case, the zero reference position of the workpiece is applied in a linear manner or as a rotation system. working measuring device, the measurement is based on This method of operation described above enables

the inductive coupling between the conductors of one that with each adjustment of the movable machine primary and a secondary winding, which is through a part, for example a button and with it These are as connected part of the measuring device, always the Operation enables a very high level of accuracy correct position of the moving machine part with respect to the measurement and control of linear or borrowed the zero reference position of one to be measured angular adjustments and distances. The workpiece that is attached to the stationary machine part otherwise common problems of aligning and counting arranged is displayed. The zero reference position with conventional measuring methods, especially with opti- 30 represents the starting point of the measurement. It consists see measurements are thereby avoided. So the task of a system of the aforementioned

It is also known a system in which the type to be designed so that taking into account the The zero position difference of the offset is determined positions relative to the zero positions or measuring cycles by measuring the distance of the position of a moving measuring device, measurement error due to the given measuring part of the position measuring device within 35 setting between the theoretical and the actual cycle to the next zero position. The moving starting point of the measurement is avoided iiche measuring part will be aligned to the zero start position.

of the workpiece or on some other dimensional In a measuring system of the type mentioned

moderately fixed point Here, an initial counts, this object is achieved according to the invention. The outer counter, which is at zero, has a layer that a first memory is provided, which has a numerical value that an inner counter, which stores the signal in this case, the distance of the first measuring part Count reduced with respect to its content to zero with respect to a measurement reference zero point will. If the inner counter reaches the value zero, and a control unit interrupts the counting during a first operation, and the content of the outer phase feeds this signal to the outer counter and Ren counter shows the position of the movable part 45 during a second working phase of the converter within one cycle of the position measuring transformer with the inner counter and the outer counter on. This counter content is combined into a calculation, with during the second work phase formula is used and from this the offset value converts the digital pulses of the count values of the counters calculated. For further measurements, it is necessary to increase or decrease a value, which the operator can adjust the calculated value so the first and second measuring part to each other taken into account for further invoices corresponding to.

Completion of the measuring processes required The movable one is in the setting phase

are. Measuring or machine part in a workpiece start

There is a great risk that operations errors occur in the position, where the measurement of this position is stored relative to the arithmetic and zero-reference position of the workpiece to be carried out by the operating personnel Control errors affect. In certain cases it is necessary to follow-up the position of the moving part of the same, to measure all dimensions again, in relation to a sin-0 position, after which the position until the position is reached at which the error offset A is calculated. This difference A occurs for the first time. These difficulties are stored considerably and are used to preset the external borrowed, since such calculations are always required when a new workpiece is placed on the machine with the zero reference position counter to the workpiece start position of the workpiece, and is used further. towards the presetting of the inner counter to the position measuring system according to the present workpiece start position relative to a sin-0 position. In the invention, several work phases are to be differentiated . Display phase before the new position of the outer counter and the display

device to be caused, the new layer member for controlling the work sequences of the system

indicate the relative zero-reference-Lagc during the setting and recording phases,

of the workpiece is measured. F i g. 8 shows an embodiment of a member for

The position measuring device has a fixed-determining the coincidence between the outer the and a movable measuring part, which arises with a 5 counter and those in the storage devices and a moving machine part holding numbers,

are connected, the position measuring device a Fig. 9 the relationship between generated in the system

Error signal depending on the mutual th signals,

Position of the two measuring parts and, depending on FIG. 10, an example of the difference between

Input control signal generated. > ° Reference positions on the machine and measuring device for

The error signal is used to determine the starting position selected,

movement of the movable part of the Lagenmeßvorrich- Fig. Π a second embodiment of an inner device over a certain number of measuring cycles and (logic) member according to FIG. 7, which is used for exercising a distance within a measuring cycle. Is suitable for choosing different control systems
Switching means responsive to the error signal generate 15 F i g. 12 is a block diagram of an oscillator with a frequency that is variable in pulse width modulus for the position measuring device and controlled by the error signal. The width of the signals is one of the system.

Function of the position of the moving machine part For the purpose of the description, various

relative to the fixed part. Further switching designations introduced. For example, will

Means are provided that the error signal to zero «o the counter for controlling the recording device

decrease when the input signals have a value called the outer counter because it is from

achieve that of the machine location within an operator from a console

Cycle of the position measuring device is equivalent. Switching elements can be controlled, which as external (logical)

When the size of the error signal can be designated via a control element. The counter that the increases in a certain value, the counting speed becomes the pulse width of the position command signals from the functionality of the system increased to a relatively higher generator controlled, is referred to as the inner counter, speed, so that all cycles of the position measurement since he is for one operator from the control panel device to be counted. The relatively higher count is not directly accessible. The logical control speed will also be used to control the internal counter during the setting phase used to reduce the setting time. 30 designated inner control members. Other parts of the

The increase in the counting speed can be dependent on their relationship works by gradually changing the to the outer, inner and parts of the operating frequency a counting signal from a specific desk.

Frequency to another frequency. Further, FIG. 1 shows, in block diagram fashion, one

it is possible to use this frequency as a function of the 35 embodiment of the system for measuring and recording

to steadily increase the size of the error signal. draw the location of a moving part of the

Logical switching means are also provided. Machine relative to a fixed machine part lengthways

a change in sign of the error signal of an axis. Although the machine parts are in the

capture and serve to create an oscillating de> Drawing are not specifically shown, goes the

last significant digits when reading and An 40 description assumes that the machine parts

show to prevent. by the designation symbols for these parts of the position

A tremor in the digital display will be shown. The measured position

changed by locking the payer after the can be read and recorded as in

Detection of a change in sign of the error- the description of a preferred embodiment

signal derived from the measuring device. 45 of the invention, or it can be used in others

and in which the error signal between "4" embodiments for creating a punched tape,

and "" oscillates while moving a typewriter. Triggering a

Part is in rest position. Computer activity, etc. are used. Even though

In the following description, embodiments are a system for measuring the position of the part lengthways

Examples of the invention shown with reference to drawings 50 of an axis can of course

described; In the drawing, the * "» «« framework of the invention also shows further systems

F i g. Figure 1 is a block diagram of an embodiment provided for each axis or shaft of the machine

of the invention, ^sem

F i g. 2 an embodiment of an in the system The inner system part comprises a pulse generator

used time and reference counter, 55 gate 1 and a reference counter 2. The generator and

F i g. FIG. 3 shows an embodiment of a comparison method. The counters are shown in detail in FIG. 2 shown. the

device (a logic! Comparator) to the pulse generator generates a signal CJC with a

Determine the coincidence between the reference frequency of, for example, 4 MHz. The signal can

counter and the internal counter, which have the shape of a square wave.

4 shows an embodiment of a decade of a 60 The reference counter 2, the three decade counters 185,

counters used in the system, including 186 and 187 , provides signals to the counting

Fig. 5 is a vector representation of the relationships signals in each decade with 1, 2, 4 and 8 binary

between the encrypted decimal conductors B, C, D for generating signals for the units U,

Pulses, which are trigonometric functions, tens T and hundreds of counts proportional

F i g. 6 are an embodiment of an internal control 65. The thousands (77i) stage 188 which is a flip-flop

member for controlling the internal counter and radio 189 (see Fig. 2), generates a binary output

generator while the system is working, output signal, e.g. every time a thousand pulses

7 shows an embodiment of an external control of the generator at the input of the counter 185 .

9 10

are coming. The count signals from each decade of the hundreds of RCT counted in the outer counter 4

Reference counter 2 are compared in the comparator 3 represent pulses.

with corresponding count signals from each An example of a typical decade counter, the

Decade of the inner counter 4. The signals from are used as the decade stage of the inner counter

inner counters 4 are proportional to the count im 5 could be is related to F i g. 4th

inner counter 4. The counting signal] for controlling the shown and described.

Counting in the inner counter 4 is in the form of The inner counter 4 receives CL "-Signaie vom

Counting pulses R, C, T on line 178 by the external control member 9 for setting the counts

inner control element 5 generated as a function of a position at the output to zero and furthermore via inner logic S.

Error signal, which in detail in connection ie an I7 / O _x signal from the external control element 9, which

is described with FIG. 4. the counting device of counter 4 during the

The 4 ^ MHz signal CK is controlled at input 6 of the position.

Reference counter 2 recorded and in signals under The comparator 3, the four comparator stages 195,

divides, which includes frequencies of, for example, 2 kHz and 196, 197 and 190 , compares the count signals generate 200 kHz. The 2 kHz signal provides an i $ from the reference counter 2 with the counting signals from the internal base count rate for the system and the 200 kHz counter 4. The comparator 3 also includes a gate signal with an increased count rate, as follows circuits for reversing the inner count in is written. In the embodiment described, a 9's complement is compared before this is compared with the reference form, the counting cycles of the reference counting 2 enumeration (cf. FIG. 3). In addition, divided into 2000 equal parts, that is, the reference counter 2 ao are provided switching elements for reversing the counts 2000 pulses per counting cycle. An example of I, 2, 4, 8 inputs from the reference counter generating a counter which is suitable for use in a simple manner for the use of the T, 2, Ϊ, 8 signals, modified for comparison with a decade of the reference counter from the outer counter, by such setting the An example of a comparator stage for the Hur

logical member that is always added is the derter comparison is in FIG. 3 shown when imm ·. in Fig. 4 shown. In other words, the logical counting of the internal counter 4 with the counting element can be designed in such a way that the decades of the reference counter 2 coincide, then one counting forces 2000 pulses before the return - positive coincidence signals + TU ( Count tens and lead, the one associated with ones), + TH (thousands) and -4 H (hundreds) F i g. 4 is a reversible counter, 30 generates as input signals to the function generator <<> that is, it can count up and down. 10. The 7i / lines are connected to one another.

The two 2 kHz and 200 kHz signals are about what is a matter of design, since the teni the lines 7 and 8 with the inner control member 5 and one coincidence signals common input. connected. '" ^the gate circuit on the function generator 10, vni

Although the thousands comparator circuit 190 is shown as 35 in FIG. 6 shown.

Part of the comparator 3 is viewed. can this Whenever the 9's complement of counting m

In a special embodiment, also with inner counters 4 connected with the reference counting over other circles of the system or from true, negative coincidence signals 7 / other circles are displayed, fn similarly (tens and hinds) - TH (thousands) and 'can the thousands counting stage of the binary counter 40 (hundreds) generates as input signals to the radio 191 with the outputs A and A ~, although these are used as a tion generator 10. The Tf-Leitcr are given from the part of the internal counter 4, also as mentioned above Reasons connected with each other. Part of another circle formed or switched The positive and negative coincidences are

_se y _n . here generally as coincidences in the 4 n-

Although the description describes a combination of 45 and «channels or lines. the one binary and one binary coded numerical coincidence signals are shown in FIG. 5 by vectors The decimal system is shown graphically with appropriate circuitry.

is used, there are of course also other functions. The function generator 10 uses the coincidence

numerical systems within the framework of the denzsignale in the Λ η and η channels for the invention. For example, a generation or development of pulse-width signals, binary numerical codes and an associated one which represent trigonometric functions and suitable circuitry can be used throughout. to the input windings of the position measuring device

Tungll be forwarded as part of the special training described, which device has management example of the internal counter 4 a counting a location-measuring transformer as in the capacity, the one cycle capable measuring device 55 prior patent mentioned technique described 11 equivalent is so that its count is the position ben includes

of the moving machine part relative to that The pulse width of the signal from the function generator

of the fixed machine part in a cycle of the measuring 10 is determined by the distance of the coincidence device represented The fixed and the moving signals, - π and + - n, from a reference position. In the kitchen machine part are represented by the Ausfühningsfonn shown with the reference 60, the signals characters 13 and 12 provided fixed and movable sine and cosine functions, represented with S and C on parts of the position measuring device 11 the input lines to the position measuring device

The inner counter 4 comprises three reversible decals are indicated.

denzähler 192, 193 and 194 for counting in binary The position measuring device 11 comprises a movement-coded decimal and a counter 191 / ηπϊ 6j borrowed part 12, for example, along a .Y-axis counting of real binary numbers; Each of the decade counters 192, 193 and 194 , adjustable in different positions or adjustable, generates output signals / 1, bar act, as well as a fixed machine part. As indicated above B C, D and ~ A ~, S, ü, ZJ, which units, tens and are indicated, the reference numerals mean 12 and

11 ** 12th

Jen moving and the fixed machine part. The in F i g. 7 described, to generate RCT and moving part 12, multi-phase windings around pulses can be used.

as a pair of multi-polar primary windings, the output signal is also passed through a

which are spatially out of phase. The fixed part 13 two-way rectifier 19 for generating a Freder device can send a continuous conductor 5 quenzsteuersignals Es . The signal has to include a multipolar DC secondary winding, the value of which is a function of that of the U device. The part 13 is connected to an amplitude of the input signal and it is connected as a fixed machine part, for example in FIG. 6 for changing the counting speed (not shown) of the machine. speed from one frequency to another than

The movable and the fixed part 12 and 13 of the io function of their size are used. Two-way equal position measuring device 11 can either be linear and the associated circuits or circular (e.g. known per se for mutual rotation. The inner control member 5 includes suitable), depending on the respective flip-flops and gate circuits (cf. Fig. 6) for the type of application of the system. Either one or the 15 of the signals e. It and the time CK. The other shape generated are preferred. ÄCT pulses are generated as a function of change

In such position measuring devices 11, the sign of the error signal e is inhibited or known that the position of the movable part 12 is opposed to an oscillation of the last sign with respect to the fixed part 13 due to the relative adjustment of a fictional number or position the recording of the secondary winding against the primary winding * o on the recording device 21 can be displayed. The pretense is considered to be in shun.

electrical degrees of measured angles are shown. The generation of / iCT pulses is carried out by

This means that the distance between three successive gate circuits in the inner control element 5 synchronously following conductors of the secondary winding corresponds to a siert as a function of the unit comparison signals ACT cycle of 360 electrical degrees, which corresponds to a ₅ and ACV of the unit decades 185 and 192 of the, for example, a linear one Distance of about reference number 2 and the inner number 4. Which equals 5 mm (0.2 in). A count of synchronization is as in FIG. 7 in the individual inner counter 4 corresponds to a movement of the described, necessary to avoid counting errors, approximately 0.0025 mm (0.0001 inches). Further logical gates within the internal

The sinusoidal reversal switch 14 has + - and - -posi- 3 »ren control element 5 generate a I // D" signal for functions to reverse the polarity of the sinusoidal signal controlling the counting direction of the internal counter 4 and into the position measuring device 11. By reversing the external counter 20 via the external control element 9 of the switching position, a positive number can either be The state of the t // D "signal and therefore that caused by a machine movement to the left or in the counting direction is represented by signals UfD _x and SfU _x on the right are controlled as a function of a 35 that are generated in the outer control element 9 during the reference specification, for example on the workpiece input or generation phase (as indicated in FIG. 11). The minus -) input as well as by the sign of the error signal e, for reversing the polarity of the signal is connected to that during the normal reading or up function generator 10 when the switch drawing phase the direction of the position error 14 is closed. The Shaharm IS of the counter is, «o indicates.

connected to ground as shown, at a frequency of the RCl pulses on line 178

relatively low or negative input signal can be changed from 2 kHz to 200 kHz as to be generated when the switch 14 is in the lower function of the mode of operation or the size of the Position is error signal as indicated by Ej.

bit preamplifier 16 is between the movable 45. A 2 MHz counting signal is used for use as part of the position measuring device and the filter 17 by the external control element 9, as in connection with the amplification of the error signal from the position slope with FIG. 8 described, generated
Measuring device 11 arranged. In the filter 17 the external control member 9 comprises a counter

all harmonics with the exception of the one in the system (counter 134, FIG. 8), which in this case is filtered out with a minimum frequency signal used. Such 50 speed of 2 MHz counts, as well as ver-filter and preamplifier are known per se and tied gates and flip-flops, therefore need not be described Input and reading phase. This is converted into a sinusoidal signal, the outer control element 9 of which generates 17 / Dj signals for amplitude as a function of the difference between 55 controlling the counting direction of the outer counter 2 (the command position, represented by sine and Ko as a function of the direction of movement the Move sinusoidal signals from the function generator 10, and the loan machine part 12, represented by dei actual position of the movable member 12 in the condition of i // D _n signal. For Aufzeichmmgs- a cycle or the measuring device 11 is. reproducing apparatus 21 is a plus minus

The output signal from the filter 17 is fed to the signal on a line marked with ± a through a phase detector 18 for generation, sent to reproduce the sign of a direct current error signal e . The number contained in the missing outer counter 20. The Aufzeich lersignal has a polarity that is a function of the voltage device 21 is connected to the outer counter 2 direction of error in the position between the, z. B. in one structural unit
movable and the fixed machine link is 65. In the outer control link 9 a «return sign; Such phase detectors and the connected RS for resetting the outer counter 20 and circuits for generating DC voltages CL _n signal for resetting the inner counter are known per se. The error signal is generated as

1 S24 426 (

13 ¹⁴

τν A "™" iopvorrichtune21 can 6 indicator tubes The outer control element 9 is even more precise in The ^AMe _f £ ^e ^; ' ^u " _(ir *" * <: rwJmalen and a

tzvorrichg

The outer control member 9 is even more precise and the display front κ ^ decimals and one Connection with fig. 8 swept. nut cold ¹ ^ ¹ "". _it includes cold cathode A selector switch 24 includes positions for open voice indicator 8 “™? ™ ™ _and drive circuits

aacbnung ÄO and playback Si / to control the sen, the appropriate_wi · decimal output

How the system works. The ones with ÄO and ΛC / be 5 to convert ^the ™stens £ _the decimal leagues

Drawn lines control gate circuits (151. FCO vom ^ "" gj ^ ij LLsen. Others 4-

152 m Fig. 8 shown) in the outer control member 9, each for the A ^ from ^ ung ^ connection

after, as the Scnaltarm 198 of the selector switch ^ 7 ^^ 'V "direction 22 and 23 indicated

24 is established and also dependent on others, SpeKje at the front ^^^ ^

ren, below Ixwrite a conditions. The 10 could justlalis ⁱⁿ "" ^{a <1}

Schallann is connected to earth so that he can use a load. _h ^ _{are Wäh |} .

tively low input signal to the gate circuits. At your Jj ^ S & K 25. Rotary switch for the

151 and 152 as shown in FIG. ^ Γ ^ Απΐβη M and 23 and display

A return switch 25 is connected to the outer Ψ "* ¹ * ™ ™ *" mill (not shown) control panel Steaergüed 9 connected to reset the outer, 5 direction 21 in £ «" <? 2 * the above must be

ren Z ^ s2 · and the display device21 on monUert. V, κ: above ^^^^ axes £

Zero when a new reference position wcn2e set "SECTIONPLANE system m 'ner * e ^ _Aasnahme,

sol !, and for setting when starting an operation, speaking number) ^ ™ ^ £ ice 2, which is

The switch 25 may be a push-button switch his generator 1 New York Convention of ™™ & * ^ ™ ζ ^> _Kings nen

arranged on the control panel (not shown). rere ^^^^ 3 ^^ £ ^ Ρ ^

is, for generating an electrical voltage in Fig.2 shows ^ei " ^e ^^ J ^. ^ comprises the

Devices (not shown) inside the Deka generator I. der e.nen * ££? £ * £ Wd7rstand

denzählSu4 Fig. 8) for * setting the device - a charge level ^ £ <*% ££ * £

results to zero. The entrance to the external control 27 and the ^Ptt

^ from the reset switch 25 is only CL loaded, ₅ Djg ^

The au *. _e counter 20 comprises six reversible De- All gate circuits, the m F i g. 2 shown smd smd

cadence counters of the type as related to nand-type. I »duncs range from

F i g. 4 shown and described. The 1-, 2-, 4- and 8- The capacitor 31 has eme ^ dung ^ re ^ ev ™

(binary-small Dec. timesJ output lines from 30 of the earth via the W, demand 32 ^ * £ * £££

Uer level are with the corresponding decade meters 28 to * Pf "« "^« ^ ¹ ^ ^

d «display device 21 connected. For the connection 31 is between the diode 331 and the

panning «use only one line in the drawing. The exit from the | g

det to represent the output lines 199 h, s 34 .st with the input of the gate circuit 35 ver

204 of the four stages of each decade. That means 35 ties

- _d ^v ' _with a frequency of 4 MHz to the

Furthermore, the output lines 199-204 of the supplies. If the output of the T counter2 is set with the corresponding i, 2, 4 and 8- ₄ o, but also when the output is connected to terminals of the storage device 22, the diode 29 becomes the starting number or position of the work - Capacitor 26 saves a piece via ™stens ^ ^ά ^ £ ^ . The output lines are also. When the charge has reached about Vl _f , then w.rd connected to the storage device 23, soft the output of the gate circuit 30 low g ^ lUM and the number 45 the capacitor 31 discharges s.ch. The output that chert, as it is during the setting ^ as in the following gate circuit 34 is now up and the output that is described individually, is determined. the gate circuit 35 is switched down, so that the

The coincidence conductors PS and OS are emptied from the storage capacitor 26. _Knni , _m ^ _{titnttl M}

devices 22 and 23 feed the outside control. The loading and unloading sequence of the condensate «« »! *

membered 9 with signals representing the coincidence between so and 3Ϊ w _ie derholt for generating a / «t of counting at the counter 20 and the outer gespei-" ignals. which, for example, has a frequency of even numbers at appropriate times during the 4 MHz. To generate a time signal * with your settings show maximum separation between the pulses and

The additional storage device 23 meg four of a minimum pulse width will include two capacitor rotary switches that are used with the last significant circuits

th decades (3 to 6) of the counter and the last of the reference counter also shown in Fig. 2 ^ t

significant numbers (3 to 6) the display device comprises three BCD decade numbers 1 «Sί, 186 and 187, 21 are connected. The storage device 22 for which are connected in series to pay for the factory gap start may comprise six rotary switches (see example pulses from the gate circuit 36 and for example FIG. 9) and a signal switch 60 of 1-, 2- , 4-, 8-output signals of each decade indicate the ter, which is connected to suitable decades of the external counter units, tens and hundreds of the received time 20, the external control element 9 and the display pre-impulses The signal switch ± is a thousand flip-flop (Th) 189, which is connected in series with the Hun with the external control element 9 via a line ISS of the earth decade 187. Other storage devices can also use the logic state according to thousand / rev; ittings, which relays, solid-state switching elements, pulses. The Q or 1 output of the flip-hop include computer memory, tapes, etc., within is referred to as a thousand comparator signal RTh in the frame of the E. invention can be used. Function generator uses the other output K

15 ■ 16

in line 7 is used as a 2 kHz base or reference (tens, units) of the reference counter 2 and the inner

frequency signal used. An example of the reference counter 4 are required.

signal is shown in FIG. 10 and denoted by R. The comparator circuit 190 for the one thousand F i g. 10 is also an illustration of the counting sequence 2 'counting is contained in the function generator 10, shown as a sawtooth signal. A signal in the loop 8 5 although it is also in the comparator 3 together with the (Fig. 1), which represents the increased counting speed of the other comparator circuit, as in connection or frequency rate of 200 kHz, can be described with Fig. 1, be included One embodiment of a reversing counter 186 could be taken from the /! output of the second or tens (7) decade. Sibling ßCD counter 206, which as a decade of the im

The outputs of decades 185, 186, 187 and _{I0 in} connection with the counter described in FIG

188 of the reference counter 2 are with the comparator 3, can be used. For example, six can

as shown in Fig. 1, connected. such counter for executing the outer counter

F i g. 3 shows an embodiment of the compa- 20 and three counters, of which the ratorkreises in the comparator 3 for comparing the each outputs A, B, C, D and ~ Ä, Ή, C, ZJ (such as output signals of a decade of the reference counter 2 15), could with a flip-flop, such as and the internal counter 4. The circuit shown, for example, flip-flop 189 of FIG. The section will be described for comparing the Q and Q outputs of the / Ä flip-flops 52 to 55 of the hundreds count // in the reference counter 2 with the representing B, C, D bits 1, T, 2, 2, 4, 4 ", 8, 3rd hundreds count and the nine's complement of 20 The NAND gate circuits 56 to 59 control the hundreds count in the inner counter 4. Flip-flops 52 to 55 when the decade is up

The ßCO length of the hundred decade 194 counts, and the NAND gate circuits 60 to 63 control

In the lined counter 4 (Fig. I) with A, B, C , D are the flip-flops 52 to 55, if the decade counter

and A, B, Γ, Z3 bezeHmet while the outputs 206 count down. The t // D inputs to the Nand

of the corresponding decade 187 of the reference 2 ₅ gate circuit 64 determine whether the decade

Counter 2 by the numbers 1, 2, 4 and 8 (Fig. I) counter for up or down counting

are descriptive. The link 38, which is placed four Nand-. In the case of counting up, the

Includes gates, the 8-, 4-, 2-, 1-off low input of gate 34 reverses through the

deal with the reference payer 2. so that the T, 2, Ά NAND gate circuit 68 is reversed so that the decade

and S outputs are also available for comparison. 30 is set to count up. In the case,

The reverse gates 38 could be part of the fact that the input to gate 64 is low

Reference 7h!; Rs 2 are arranged, or both the logic output is high and the decade counter 206 is

schi-n states could be from the decades set to counting down. Each of the flip flops

Form the He / ugscounter 2, can be taken from 52 to 55 can be reset to zero by

I> he combinations of the NAND gate circuits 39 35 a /? S signal, which through the reset switch 25 to 42 lead exclusively to normal circuits, is generated when the decade counter 206 is part of the comparison of the internal counting with the reference external counter 10 is, or they can be repaid. When the correspondence between all of them is established by the reset signal CL _n when input lines of the hundreds of decades of both the decade counter 206 is part of the inner counter 4. The counter is complete, then a 1 value appears at the f // output. are on line 69, which starts with RCT or CR Y IN

The combinations denoted by Nand gate circuits43 are received. The decade to 46 could form an exclusive-nor circuit for the first stage of either the outer counter 20 or the same of the 9's complement of the inner counter inner counter 4 and therefore for receiving with the reference count. The ^ complement of the 45 of the ΑΓΓ-pulses could be suitable, or it could be a count is achieved by logical processing next stage of one of the counters 20 or 4 and the certain outputs of the internal counter 4, as further half described below for receiving the lead or carrier . impulse CRY .

The AND gate circuit 47 in combination with the NAND gate circuits 70, 71, 72 and 73 he NAND gate circuit 48 supplements the most significant 50 generate a suitable output voltage for switching or most significant bit D of the inner counter 4. th or toggling the flip -Flops 52 to 55 of the Deka-Nand gate circuits 49 and 50 in combination with the counter 206 from one state to the other, the Nand gate circuit 51 complete the next signi- The Nand gate circuit 73 supplies the next fikantc bit C des inner counter 4. The ß-bit does not change (not shown) decade with a carrier pulse in its supplemented state, and the 55 CR Y OUT.

A-BH is supplemented by reversing the inputs of the In the particular embodiment shown is a combination of the NAND gates 46. Therefore, the AND gate 76 has been added to determine when the decade counter is used instead of A with i as in the gate circuit 206 has a zero combination 42, to compare ~ Ä with T, as in the count. The ability of detecting the NuIl-Nand gate combination 46 was compared. 60 position is from the outer control member 9 to the deter-

If the case of coincidence between the limiting of the setting of the UID _x signal, as in

train counting and the 9 complement of the // counting Fig. 7 is used. more details

occurs, then the logical 1 value appears in connection with FIG. 7, on which the

passage of the - // - channel. Both the + // - and - // - off outer control element? is shown, described and

are shown connected to the function generator 10,

bundcn. Assuming that the decade counter 206

Although only one comparator circle is shown, it is set back and the UID ratio is large,

It is obvious that further circles for each decade then causes one at the input of the flip-flop 52

17 ¹⁸

17th

received signal that the Q output is high retracted position by an additional interval of 500

will provide. No other flip-flop would be set offset Generate

because the Nand gate switching elements 56 to 59 are created by the function generator0> is used to generate

ili 55 dl S ^nale % ^ ' ^c ^ ^inus " ^nd

because the Nand Torschaltumiea 56 to 59 by D

the zero setting of the flip-flop 52 to 55 before the pulse-width analog S'S ^nale % ^ ' ^c ^ ^inus " ^nd

Reception of the first signal. 5 represent cosine functions ^ s funcion ^ r number

On the basis of the reception of the next input coincidence between the ^ fgj ^ ² <i ^nd

l il 52 i d ieen payer 4 The P ^

pg gg lungs coincidence between ^ fgj ^ i

signals, the ß-output on the flip-flop 52 changes its internal counter 4. The P ^^ th signals can change state from high to low. The output of the NEN as position command signals for the ^La SeMeßvomch gate circuit56 is high and represents the outturnll be viewed

state from high to low. The outcome of the nen as gg

Gate circuit56 is high and represents the status being viewed »

The output of the gate circuit 70 is low when receiving the function generator is in the

Start of the next pulse of the generatori (RCT legungsschnft 1 956 881 ^b " ^cnneDe ";. _; _ _np , _pn

or CRY IN) to set the Q output from the F i g. Fig. 6 shows an from ^ "mg ^ ⁰ ™ ' ^d « J ™ «™

FUp-Flop 53 on "high". Control member 5 including inhibiting or locking member

The sequence of numbers is continued until the decade 108 for blocking or intaügkeitkeit Setting the und counter 206 contains the count 9, at which time the> ₅ gate circuit 104, depending on whether the error output of the NAND gate circuit 59 is set low, signal e the pre / calibrate as the result of the last application. The next counting pulse then represents the ß-austerity of the inner counting changed nai. The output of the flip-hop 55 goes low and produces an Assume that the error signal of the previous carry output from the NAND gate circuit 73 on the count was positive, for example. From this fb.gt, the next decade (not shown). *> that the i / ZD line from flip-flop 104 goes high

When all Ö-outputs are high and that is. If the next error signal changes from

Show zero condition ZD , if the Nand gate scarf positive changes to negative, then the > υιυ-ιχι-

tung74 is set to low and the NAND gate switching from high to low

tion 75 to high. When a null condition for a switch. .

previous decade is determined as by »5 The AND gate circuit 106, which is a part of the

If a high signal is displayed in the ZD-W conductor, the exclusive (or sole) Nor circuit IU7 is surrounded.

Output ZD-OUT of the AND gate circuit 76 to one receives input signals from the Q flip-flop 1U7 and the

next level high. ß / D line. The AND gate circuit 109 receives em-

Fig. 5 is a vector representation of coincident output signals from the output Q of the flip-hop IUJJ and

Signals or pulses, where + n and -n from the 30 of the V / 25 line.

Comparator circuits of the system (see. Fig. 1 through 3) Since the I // D line was set high for

be generated. Receipt of the last error signal, Q medng

The circle (360 °) represents a cycle of being and Q high. If the t '/ D line is the result

Reference counter 2, which goes down with reference position »zero« when the error signal changes,

begins. In the assumed example, the circle 35 is then the output of the Nor circle 107 is low

divided into 2000 equal intervals so that each interval and the output of the AND gate circuit 104

vall or every count is equal to an angle, be locked.

measure from the reference position. For example, if the inputs to gate circuits 106

a count to "1" in the inner counter 4 is the same and 109 have not changed their signs,

an angle of 0.18 °. As the count increases to 40, the output of the Nor circle 107 will be high,

the angle represented by the count would change and the AND gate 104 will be able to

enlarge too. the next ÄCT pulse to conductor 178

The pulses represented by the vectors are passed by the AND gate circuit 110 of the are on both sides of the reference position in the same ÄiT-pulse generating member 111. Hs is to be-distance arranged to avoid errors caused by the inevitable 45 that the gate circuit 110 also wanted an input Receives phase shifts in the system verur- signal from the NAND gate circuit 118, are gentle to eliminate. Phase shifts in which itself the 77, -pulse from the and-gate scarf system cause both pulses to shift 137 (FIG. 8) reversed. This ensures Exercise in the same direction relative to the reference position. that the ÄCT impulses are mistakenly not to the same As a result, therefore, the pulse separation and 50 time remain that the biquinary counter 134 continues the command situation (command-compliant position) also switches.

the same. Additional Methods for Generating The output from the AND gate circuit 114 toggles from waveforms that correspond to the sine and cosine, respectively, the flip-flop 108 in such a way that its Q and g are log-out and those at one of the processes described above States of the U / D and U / 75 lines applicable to alternative systems are shown in Fig. 55 at the time when the last KCT pulse generated the USA. Application Ser. 645161, has been registered.

on June 12, 1967, for a digital-to-analog conversion. The KC7 "element 111 includes an AND gate switch converter 112 for toggling the flip-flop 113. The off-other signals or pulses passed through the gang of the Flip-flops 113 controls the output of the vector -n + 500, + n + 500, - «+ 1000, 60 flip-flops 114. The output ¹ Q. from flip-flop 114 +« + 1000, - η Λ- 1500 , + η + 1500 generates an input signal for the gate circuit 110. are also generated by the function generator 10. The other input comes from the Q output of the. By suitable selection of the pulses, flip-flops 113 can be generated.

Generated pulse widths that are analogous to signals. The if input is connected to earth. Dei

which trigonometric functions in the 65 Q output conductor of the flip-flop 113 is with reference

describe different quadrants of a circle. sign 210, and the / input conductor to the

Although not shown in Fig. 5, as in flip-flop 113 is denoted by reference numeral 211,

10, each pulse width signal from the input line causing the triggering to the

19 20

Rip-flop 114 is denoted by reference number 213. If the -η count are generated, then the input to the flip-flop 113 that triggers Oer is denoted by + n count also in the opposite j * ¹⁰¹¹¹ ™ ⁸ tugszeichen 212 . The exit of the gate- changed. Both counts are ^{1 s} y ^nc r " ^o ! LfΓ circuit 112 is set high when receiving changes or changes, and rough ^ on; ines time signal CK, the 2-kHz or 200-kHz errors are avoided. .

Pulses from the high set £ J output of the flip- Assume as a specific example, aaL ac

Flops 113. The g output of flip-flop 113 is internal counter 4 for counting back from a camouflage still set by the output of frequency 0001 is set. The U / 25 line is said to be high in the control circuit 115th . If the reference counter 2 em-

If the error signal holds or performs below a certain to, then the output is of aer amplitude, then results in the relatively low Fie Exclusive-Nor gate 107 set high, urra quenzsigiial 2 kHz the input signal to the flip-flop when the reference counter 2 a count ^ ^enma / ¹ ' 153. However, if the amplitude is a given then the output is set low. The high would assume that the output from the NOR circuit ^{1U /} J " ^C ™ frequency signal is also blocked during the setting phase, then the gate circuit generally generates a. As shown in FIGS. «CT pulse to lower the inner count by ncn by changing the element or the circuit that completes the i.

viihlsignale, which have higher frequencies, but when the inner counter4 to after-oD-

»Beside the working speed of the system» o counting from a count of 2 was included, "Be turned. then the nor output would be set high

At the flip-flop 114 there is also an input signal from the clock circuit 116 when the next following AC input is received. The flip-flop 114 ses from the reference counter 2 and the RCr-ltipuls were W ₁ , ii triggered by the signal from the synchronization from the gate circuit 104 when receiving the response 116 to terminate a KCT pulse, a ₅ sien the following l-Cr- Completed the impulse. when the sync signal goes from high to low When using the 10's complement to ateue

switches as a function of the counting direction of the inner of the 9's complement, there would be no odd number of counter 4 and the relationship between the input counts between the - «and + n counts, una small 1 CT and 1 CV from reference counter 2 and it would be possible to find out successive coincidences from the inner counter 4. 30 for a channel and coincidences

The synchronization circuit 116 includes the exclusive in the other channel, depending on the connection in the Nor circuit 117 with the inputs 1 CT and 1 CV; which the inner counter 4 counts completely from this one generates a high output when both admit. ,

Cangs match. If both inputs are not The frequency control circuit 115 includes the wanu

To match. the output is low. The gate circuit 125, which SU " ⁿ ^ - (™ fJ» ™? 'Output is reversed by the NAND gate circuit signals from the external control element 9 or the uieicn- 120. The exclusive OR circuit 126 generates a judge circuit 19 receives.

high output on the flip-flop 114, if its one is usually the «7, -S.gnri while the fcin-

courses V10 and 120; UID and 117 mismatch phase are set low and in the rest of the time men and a low output if the input 4 ° is set high. The ES signal is «« »nnalerwewe gangs coincide. The inputs UID and U / 75 are set high and are then n.edng when the value is generated by the flip-flop 105 , whose off or the size of the error signal is connected to a predetermined input 184 to ground, so the value exceeds. ...... _nn ,:. ". _{at the}

that its Q and ^ outputs by enabling- If either signal is low .then, cherishes am

signals and the presetting signal P from the Nand 45 output of the gate circuit 1 25 «ne Johe JP ^a ™ J gate circuit 207 or the AND gate circuit 209 , and the Nand gate circuit 126 hef, rt the signal are controlled with the higher frequency 200 kHz to the flip-flop

The NAND gate circuit 207 is partly controlled 113 by the NAND gate circuit 127. by the NAND gate circuit 209, which the error when both input signals to the gate circuit

receives signal e (sign) and is set with the input 50 high, ie. The Xnd gate 208 went under high voltage connected. then the signal runs with the longer η

Therefore, if the NAND gate circuits (Nand gangs from the Nor circuit 107 , the RCT gates) 128 and 127 to the ^ flip-flop , 113 are not assumed to block the off frequency. Pulses at coincidence between 1 CT- and 1 CV- During part of the setting phase it is necessary ^

Counts creamable. if the inner counter 4 is manoeuvrable after 55, the counting device of the inner counter 4 orn counts up, and in the event of anti-coincidences between the outer counting elements 9 to be controlled. The logic element counts when the inner counter 4 goes down 129 (Fig. 6) supplies an output signal Ü / P “to count. Otherwise, it would be possible to determine further correspondence control of the inner counter 4 both during these moods when counting upwards part of the setting phase and during the normal and such agreements when ^counting downwards. Pinstello bunny

Miss count and therefore incorrect information about when the Sl ^ ^ r signal during fcinsteHphasu

_crzeueen is set low, then the output of aur

Note that the -n or 9's complement NAND gate 138 is high. ^. £ W ™ ^1. ^ Counting an inverted or opposite Po- Nand gate circuit 133 is. '^ Otherwise Λ och. ^ e 'larity or parity with respect to or for the + «counting circuit 132 is therefore high when d has. For example, if the inner counter 4 is a 1 signal UID _x high, and force !. Une A «twan counts, then the 9's complement would be 1998. If im counting If UID is low, then the result is RCT pulses for carrying out the gate circuit 131 set high and oie ™ n

I 924 426

nmnrftnh in cine z & brag the

, ie SXi ₁ IMKiI, βο that

\ der Pwnarflgag der i ^ ö-Leeaag vom F% -Ro5 »M5Sherdi £ N ^ i-TorBcl» akaBgU3MgL

Fig. 11 -Jü ^ p »j4np MtaiBfflrartinm des mUi

S & eaeigaedsS, wetdhes im Zasaannenkna · mfl Fig. 6 bcb wBsdc The Aafifaaraw] tu gsraäß Fijg. 11 sfeia the MqgSrMtfät des Umediaätens from Sashareqaenz voa 2 kHz to 1 IfHz asstaa 2 aaf 2m kHz. Dto Rp ^ ti «» 115 FiE. 6 et aa '******* the Tea3 m dor ajeaaderl tsL The yj »niwrtr

r Ovrifljunr 2K5 "can be a

P PmDOCTCK & JSHW VQBiBT * liT * ff ff P. HOT ¹ "

fassm, dk atf the Sicuersigaal ES is äbgesämmt. Stikäe St »eroszaialorc & smd an sidi bekaani.

s Wean the value of the gS ES via cmen If the specified value increases, the switch. aostaa from SNUJfe-S & ial direct «rf the J-MH? - Signal nmrmdialtea, dnc sokhe Fnsqncn? airf modes, which from the function of the larger error signak

■ äaraeriia & cäies & enadis vco aagewanaieaefl 20OkHz be 1 MHz aasfcigL The Frcqacaz of the Awsgang signals wire dana eae Rnfttioa the Gi ^ c des

The Rp-ffcfK tiy "usdi44 ^r ^ d ^ ü dea R ^ h q» MJ aad IM fFig. 6) idaend. Mn the carrion Fig- 7 Sieaeqdied

^ u of the outer

or the »« ercn ioghehea Schatnmg ■ iqaua counter 134 is in ReAc DekadeatSUeraB, CDi Naad TorschaltB «135 raised

wad. Aadocraeüs wad d »9ΓΤ-abscUossea _ ■ «. <. WW ₁ RückstcOschahcr 25 (Fie I) «eosidlea des counting 134 aaf a ZaUaBg> n« as the nonnafc Zähferanzage aasqgt. The return ticket will also be at the beginning of the Emsteu

zn dea F & p-Fiops llT md igaage ^ Hq ^ flolO

igaage ^ Hq ^ flopslO »Dk Torscfatoogca 112, Fig. 6 gczagl. The EiagaBg / HopJOBefart Tdb

md F & p-

ndiabaagcallZZtTBadS The Kaad-ToTfdaliiiag tM

the l-MIto-TT the same MHz-ShSeepehe terf ^ Anch die Tors *: * 5 tong L * as FnnktM, the counter «» »m counter I. D «* e K ^ poopuhc«. Ζ »^! ^^^^^ B-Oekade "stan jar>" - Oekade bKaaairea ZaUers 134

V "S ^ ade, the" logocner Stat "tem 3c doe Fv & tins: »ar tough

Boiagaaga wk d> e ^^ Tomtoli ^ l »^ 200 ^ Hz-Zea» gi »i rar Naad-Tunrfaiiang 12 · ge« defect hat Das, Emsseifeaeoers ^ iaS SV, yefen a wl n. The Naad gate ^ itongeB 12T and

Feöfcr-

Toncaaftaagea 12T and 126 as ooeen , m Z ^ am iwahaag am Fig. 6 beschncbra The 2 ^ Hz Bezaga signal R celebrates em Egapa to the NanJ-Tor-

g l ^ TorsS ^

nut der Uod-TorsdtaltoBg Ut o the Fmg * ^ to the TTnd Torscfeafcaog 137 rfk twv cnjeMdH and. dana can do the 2 MHz S «! nal du ·. ss dk gate circuit 13 «tuadmm *« ta »3l · Dae '-MH Signal wmi for the given example now ziföh π

^ ^ ¹ "»? « ¹ « «'« π «ZI""134 to the Vert« T> de emer laerfercw «« ctoeo the J ³⁴ «ί« «*« «Za ^ n 22 des

Wätoead der F ^ eHphase finished »Ä ^ Hz-Zcitagnal em EaigaagcsigBa] zer hmzugefOpen Torzaheng 2t2 \ wekaes den * d» Sl ' ₃ -StgnaJ there * ¹ T u

The Naad-Torscfaannng 127 was replaced by the And-Torezcfaitang 12T. The output of 127 * together BBt the output Q of the fep-flop 114 '

"Fb ^ nopl" te d "NaodT" ^^ 2t4 zaracLDerAtisgaag ^ OnderUnd-TorsdiallBsg 12T upper the Nand-Torsdiahang 2t3 'Sefert also a signal to the entrance / of the Ffip-FlopίΙ3 \ so that the next Zerömpak, aadideni the Torsdialoing sfcäi hoc * dns ^ U, the beginning Q anfladlLWenDderABSgangßdesFnpFtopslU ' 1 »ah Ae maximum Gesdiwndekert. bo the other ZaHer iMen can that '

Signal "TTddnncfi die Naod-Toncbaltmec 2"<& n, F, g 6 geze *,, STSS ^

al * answer to em UT-Smai and d "der And-Torscfaahung Ht ^ _{/ c} D" Nffld-ToRchatamgen 13 ". 13 ». 14 and 141 (FIG. 7) return the oopscbea) state of the augments on the counter decades on εεαετκ

5 · Incoming saga for dss Dciocbcrrhcd bndx D

Sieaerkreis », like b> the one described, zn etzeagea. i d Brib

is low. then the FSp-FKIP ll-f zaröckge "sd is. The rest of the tea of the Aaäcbning ^ orm according to ^: ~ 'bteibea unchanged-

n, zn etzeagea.

At the beginning of the operation of the system, the RäckstellschaltungT25 is used for a Zänhing ^ n 9 or dra modns or "Se Zafcranzeberpb"

Se Zafcranzeberpb «Oppressed Baraoffaia begkaa the counter 134, when the phase viewer the EinsteOohas

g-O btebea in the v «changes Fig. 12 shows a comparison of the BkxidiagraHEa £ llnMdificieTtoi Affifammgöorm Der Sfsan

gnal EIS as a SteaersjgBaJ and delivers an A9sgangsagoal / ni with variable frequency

'Nand-Torsdt be wfiwfrt.

hanging

Schaher removes the EinsteOohase »~ ic «O lang zhhi VervoIbtiiKBgea the Ein ^ elMiase.

The decoding duiltang amfaSt eme Nasrf gate splitting 142 znai decoding the Zahhmeen 0 ^ ⁵ ****] **** & * «les RädBleas ^ nak CUt to the named Z2fler4. The Tl42 receives Bn * s gang signaie from the NaodTdi 1 «1»

of Fig.

who from the gate circuit 136 above the diode ISS this Highly valued socially vednadert Strjrsanak «na"

incorrect decoding that can occur when decoding counters 0 and 5. The output signal of the gate circuit 142 also generates an input signal to the AND gate circuit 144. The AND gate circuit 144 receives the decoded counts 0, 2, 5, 7 and the CL signal from the push button switch 25 to generate a reset signal CL _x which outer turn counter 20 goes. The gate circuit 144 receives input signals from the CL line, the gate circuit 142 and the gate circuit 143. The gate circuit 143 receives input signals from the gate circuit 140 and directly from the Γ-stage of the counter 134.

The SU _x signal in the internal control circuit 5 comes directly from the D stage. It is set high for counts 4 and 9. Otherwise, it is set low and indicates the setting phase.

The direction in which the inner counter 4 counts during certain periods of the setting phase is controlled by the UD , signal from the gate circuit 145, which also sends a presetting signal to the tlip-flop 146 and a reset signal to the flip-flop 147 of the C / D ^ Control circuit generated. The UID _x control circuit controls the direction in which the outer counter 20 counts. The NAND gate circuit 145 is coupled to the CL _x output of the gate circuit 144 via the diode 130 in order to ensure that the counting direction of the internal counter 4 is not erroneously set during a reset operation.

At count 4, the NAND gate 151 is set low since the RO line ho-h is set isi. The Nand-Torschaltunpen 153 and 154 are high is set so that NAND gate 148 is low and NAND gate 145 is high. As Ergtb When the gate circuit 148 is set low, the flip-flop 147 is prefixed high and that Flip-hop 146 reset.

The state of the UID ₀ -I. Calculation during count 4 is passed to the output of the VID , line so that outer counter 20 follows inner counter 4. As will be described below, counters 4 and 29 count the offset number (offsct -Number). For this reason, the outer counter 20 must follow the inner counter 4

The NAND gate circuits 149, 158, 151 and 152 decode counts of 1 and 8, 6, 4 and 9. Each of the gate circuits 149 to 152 receives suitable input signals for effecting the decoding. For example, the NAND gate circuit 149 receives a signal from the NAND gate circuit 158, which has inputs from the NAND gate circuits 156 and 157. The gates 156 and 157 receive inputs directly from the A and C stages and from the reverse outputs of the C and Λ stages of the counter 134.

Since the counter content has a plus or minus sign at the start of the part, the internal counter 4 is caused by Cr pulses from the internal control circuit or the internal control circuit 5, that during counts 1 and 8 it goes up on a negative number and up on a positive number Number counts down. During count 6, both counters 4 and 20 count up.

The coincidence signal PS, which describes the starting position of the part, generates an additional input signal to the NAND gate circuit 149, which also has input signals from the B stage of the counter 134 and gates 138 and 158. Both Counts I and 8 becomes the state of the Ρλ signal reversed by gate circuit 149. If there is a coincidence, the output signal is high and the gate

S tion 137 also set high. It can be a a new count can be made in counter 134.

The offset coincidence signal OS generates an input signal to the NAND gate circuit 150. The counter Record signal RO generates an input to NAND gate 151, and set signal SU generates an input to NAND gate 152. When counter 134 has counted up to corresponding decoding counts, these will be

Gate circuits 150, 151, 152 controlled by the state of the input signals.

The (logic) circuit 216 generates t // D _A signals and + signals as described above. The! /// ^ control circuit includes / K flip-flops

146 and 147, which have toggle inputs from the RCT line and from the AND gate 158. The AND gate 158 receives input signals from the AND gate 159 and from the ÄCr line. The AND gate 159 is high

»5 is set if the outer counter 20 meets the zero condition ZD and if the output of the NAND gate circuit 151 is set high, ie. has a high level of tension.

The NAND gates 160 and 161 control

the ♦ displays of the display device 21. The NAND gate 161 reverses the output of NAND gate 160. The Nand gate circuit 162 receives an input signal from the gate circuit 159 and generates a low input for the Adjust gate 160 when outer counter 20 has a zero condition. To the rest Times are the ± gate circuits 160 and 161 by the state of the 0 output from the flip-flop N »? as a function of the state of the IZ / Dn line and the passage of the outer counter 20 through zero and therefore controlled from one counting direction to another. 1 in signal in the line marked with ZD indicates when the counter 20 is at zero.

* 5 ^ ^he NAND gate circuit 163 inverts the signal in the l // D "line and generates an output signal to the K input of the Fhp flop 146, the Nand gate circuit 164 and the NAND gate circuit 165.

If the l // D "line from the inner control

circuit 5 set high for counting up then the NAND gate 166 sets the NAND gate 167 high. When the l // D “line is set low for counting down, then the NAND gate 165 gates 167 low a. The output from Nandlor circuit 162 is high. It is believed that the flip-flop 147 is in the state of logic one so that its ß output is set high and its Ö output is set low.

The NAND gate circuits 164, 168 and 169 control together with the gate circuits 158 'and 15! the flip-flop 147, so that the state of the UfD _x line is changed or changed depending on the state of the I // D "line. The output Q from Flip-hop 147 controls the sign of the display device 21, as indicated above

During normal display or recording operation hn state of the count 9 of the bi

409613/29

quinary counter 134 , the i // D "state is passed on through the circuit to the l // D _{t line} . This justifies the assumption of an input to the gate 154 so that the gate 148 sets the flip-flop 147 beforehand during the eight count. If a (logical) zero is detected by the gate circuit 159 during the down counting, the next / "C7" pulse causes the flip-flop 147 to toggle and to reverse the relative direction (counting direction) of the outer and inner Counter.

For example, let the inner counter 4 and the outer counter 20 be set to count down during a measuring operation. When the workpiece (represented by the reference numeral 214 Λ in Fig. 10) assumes a zero position, it may be necessary to move a button (shown by the reference numeral 215 in Fig. U) on your movable machine part, for example to move it through zero, without reversing the direction of machine movement. The outer counter 20 has a + indicator 21 'so that it can count through zero while the inner counter counts up or down. Circuit 216, described in the previous section, is used to reverse the counting direction and sign of outer counter 20 when a zero condition is detected. In this way, the displayed dimensions increase with the sign ± on either side of zero. A summary of the decoding operation during the setup phase is shown in Table 1 below.

Table I.

Biquinary counter
ABCD Decoded
count CL _n and CL _x (inner and outer counter back
placed) 0 0 0 0 0 PS signal, in the outer and in the inner (on
if + and down, if ■ -) counter paid 0 10 0 1 CL _x 0 0 10 2 no activity 0 110 3 Servo (outer counter with the inner counter in
Counting and direction connected) 0 0 0 1
(calculated and displayed offset
Number; the operator provides
the offset number on one turn
button and the phase switch
on ads) 4th CL _n and CL _x 10 0 0 5 ΟΓ signal, in the inner and outer counters
counted 110 0 6th CL _x 10 10 7th PS signal in the inner counter algebraically with the DV
Signal added; PS signal in the outer meter
counted 1110 e Normal display 10 0 1 9

F i g. 8 shows an embodiment of a simple logic circuit, shown as circuit 170, for detecting the correspondence (coincidence) between a decade of the outer counter 20 and a CD switch of the parts start memory device 22 or the parts offset memory device. Apparatus 23. Circuit 170 is included as part of workpiece start or offset memory devices 22 and 23 shown generally in FIG. Similar circuitry is provided for each rotary knob switch of both memory devices 22 and 23, as well as for each decade of the outer counter 20. The circuitry is only effective for counting in one direction; a full decode circuit would be required to count in both directions.

The ßCD rotary knob switches 22, 23 are set by hand and display a selected number. The number on the workpiece start storage device 22 indicates a starting point on a workpiece, while the number on the displacement storage device 23 indicates the displacement number. A mechanical connection 171 extends from the illustrated rotary knob to the switches 17i to 175. The Switches are closed or open depending on the lie of the rotary knob 22, 23.

Before the coincidence is reached, the closed switches are grounded in the external counter 20 via one or both diodes 176 and a switching device, such as a transistor (not shown). The result is that the voltage V ₁ in the resistor R drops and at the input to the NAND gate circuit IT, is low

Lina auge: ».! Luuvi. w · »....... .— _o _. ... _{B. w}

this rotary knob switch 22, 23 is set high for gate switching.

For the particular embodiment shown, if all inputs are to Nand-1 "'■ - · · -, then there is coincidence between the
Counter 20 and the one on the Spcicl

set position is displayed.

from gate circuit 177 (either PS or OS)

fet with the external (logic) circuit 9, such as

- ■ '■ - ^w - ^u: -' «-« with Pi ο 7 nezeiet and srssr

_{switched) and} the inner counter 4. _The counter 20 is automatically increased ^and _{then the} counter 4 and 20 count to the starting position _{indicated by the rotary knob switch 22 * \ fe} ζ . _The inner counter becomes 4

forced to count with the ⁸ m outer counter 20, ge ^ g, _{rf has} capacity. For the

although w ^ f _{O execution} rm, the

ρ _2ooo ^ " _over ^ _{target range}

Assume that a workpiece or part is in ge suitable manner on a machine ^ tfjgg "" and that the dimensions of the value stuccos .to measure and vergWen with as provided in ^ r drawing dimensions jnd Ue adjustment phase is used to FesUegen the difference between the reference »" ^ » ^k * * £

Workpiece on the machine and ^d ™ & _n point of the position measuring device 11 and to the exact

Setting the counters 4 and ZO.

In the setting phase, the

Machine, e.g. B. cm button (| ^.; Fig. 10). manually as exactly as ^mo 8>. ^IC J "LJ" * Start _P osit, on the workpiece (Be.ugsmchen IUA, Fig. 10) set manually.

After the machine truck 2 »5 dumped the loading

Servant in a ί ^ * ^11β " _η ^ 2 £ SnS! - was placed, w.rd the corresponding Ujmen

en manually on the part
on the control panel

The parts start position «^ point 214 correspond, or mc can cine

£ ^a5

³ ° _the ^H display device 21 +0.5, ^^ "d inner counter 4 contains 12Ml The _h , _l34 then increases its payment biqu nare ^ ^ * _{rfer outer} ^^^ _{au {}

u ^ i _urüc kgesiem. The biquinary counter 134 mm makes g _{and e} ^ _{Tough, clothes}

] ^ ^ " _ηη6Γεη counter 4 is converted into sine and cosine _Ana w _S ignale, which amplitudes analog> g ^ ^ ^ ^. ^ ^ _{by the}

proportional angle shown are the position of the probe 215 is not to of _the signal _h representing position correspondent ^ then a Fthlersignal able-measuring ^ w ^^ then _the ^S _Fe hlersi _i; nal causes counter 4 to count until the error signal from casting device 11 becomes zero. If the error signal is zero, then the payment in the ^K _{counter4 shows the correct} position of _{the moving ^ Vi 15} 12 in the working cycle of the measuring device - that part of the position

_of said button 215, which is within emes S position measuring device 11 The number

^ Counts lays out the difference between the

rgeSUtunraTden, Werk ^ from which to measure the workpiece dimensions

are. ... ,,. . . _iap

21djMj _S

ewegl, che ^

For this

DieUnfc2IS (^ _i
a button or another

Example became one

.0, 123OZoIl, measured under. ^ ™ * ^ 5 of the part zero point 214, selected. In other cases, ^P could be chosen to be a negative number. The zero positions of the measuring device, which are arranged at symmetrical intervals, are also shown in FIG. 10; Sf

% & £ £, _20, tan _{is simu rubbed} with the inner _and outer Anzeigevornchdem _since the counter 20 follows is the differential ^ J ^ * ^ _the ßezugs zero Lagea on the _{pointing device 21} to _geze i _g t. This is d, e relocation

h, ^ ^ _hme ,

the button at 0.0WOZoIl within a circle

Position measuring device 11 is arranged. it holds that location Meo β _Q9QQ ^. ^

f means that the counter4 is around

TVJ _ώΜεη ^ rde and the passing pulse nachgj »^^^ ^ ^^

ΐ would count. The number 9670 represents ^ --number ^

₅₀ that
the

gOt,

^ of

Vornchtur, ^ H

Ϊ2Α _P g

Link 12 at a distance of

one of the «m-0 positions of the

is arranged if one had

sions from a reference zero point>

Corresponding m, t one of the sine zero positions. 0

nen, then the movable link would be 12 nfm «« 5 ^ ₁₆₁ . _{134 advances} to 5 ^ _{(4 and 20} ) are on; Noll back ^ _{ells The biquinary} counter 124 increments to 6 voi ge M ₄ ^ ^ _{can count up} ,

uncMne Versetoings-Knob-Scha]

Pay the capacity de

Count 1670 ends when outer counter 20 and the offset knob match switch 23 is achieved.

After the match is reached, the counter 134 advances to 7, where the outer counter is reset, then to 8, where both counters 4 and 20 can count to the factory start number indicated on the workpiece start rotary switch 22 . The inner counter 4 counts simultaneously. Since the number exceeds the capacity of the internal counter 4, it is reset and ends with the sum of the two numbers 5, 1230 and 1670 or 0900, which is the current position of the button 215 within one cycle of the position measuring transformer 11. The workpiece start position is displayed on the display device.

This operation is summarized in Table 11 below, which shows the contents of the inner and outer counters at each step of the adjustment sequences. In labile II, the step number corresponds to the decoded count of the biquinary counter 134 (as listed in Table I above). The values given for the contents of the inner counter 4 and the outer counter 20 correspond to that in FIG. 11 shown example.

Table II

Setting step number (decoded state of the biquary counter 134) Workpiece start switch 22 set to +05.1230 everywhere, offset switch 23 set to 9670 at the end of step 4

r State of the internal counter 4

I r- state of the external counter 20 (always + for this example)

task

0 0 0 0
12 3 0
12 3 0
0

12 3

0 9 0 0

0 0 0 0

16 7 0

16 7 0

0 9 0 0

0 9 0 0

0 0 0 0 0 0

0 5 12 3 0

0 0 0 0 0 0

0 0 0 0 0 0

9 9 9 6 7 0

0 0 0 0 0 0

0 0 9 6 7 0

0 0 0 0 0 0

0 5 12 3 0

0 5 12 3 0

The inner and outer counters are reset to zero Counting to the parts start position

Outer counter reset

No activity

Servo to zero

Inner and outer counter reset

Counting to the offset position

Outer counter reset

Counting to the workpiece start position

Servo at zero - stays until the machine moves

When the normal course of the display phase begins, then counters 4 and 20 become appropriate Point to the beginning of the count either up or down, depending on the path along which the Button is moved, set.

Every time the 1 aster 215 is placed in a new position, this is indicated by the display device 21 .

The operation continues until all measurements have been taken.

Interruptions can take the form of deliberate shutdowns, such as at the end of a normal working day be made or in the form of unplanned or unwanted shutdowns that then occur can, if the energy fails or due to some other occurrence that a Switching off the device conditionally.

In the event of a planned shutdown, work can very easily be resumed without having to repeat the entire setting phase. in one particular case, the last dimension indicated is transferred from each axis to its part start knobs 22 , etc., and the system is shut down. If the resumption of activity or work is desired, then the system is switched to "setting" until the display device adjusts. As a result, the selector or phase switch 24 is switched to "Display" without changing the rotary knob switch 22 , and the measurement is resumed.

After the resumption of the measurement, the visual display device 21 should display the position set or stored on the workpiece start rotary knob switch 22. If the machine was moved away from this position during the switch-off time within plus or minus half a cycle of the position measuring arrangement II, then the display device will precisely indicate the new position.

In the event of an unplanned shutdown or failure, the operator can resume normal work without extensive adjustment measures by measuring the position of the button 215 at the time of the failure within half a cycle of the position measuring device 11, for example 0.1 inches. The position is set in the workpiece start knob switch 22 and the phase switch 24 is placed in the set position. After balancing the display device 21, the operator switches to the display phase and continues with his normal measuring activity.

An operator often wants to know the position of the probe 215 within the cycle of the position measuring transformer 11.

According to the present system, the next zero position or sine zero position can be determined by switching on the setting phase with a zero workpiece start rotary knob 22. The inner counter 4 counts on the position of the button 215 in one cycle, and the outer counter 2ff will follow. The outer counter 20 will then indicate the distance of the sample 215 from the nearest sinusoidal location. The button 215 can now be turned into a sine zero

31 ^ ¹ 32

Be brought into position by moving it, (between cycles of the McUelcmcnls and the coarse

until the display device 21 counts, the frequency can be increased

Showing thousands in its last four digits; this will also be, for example, 1 MHz. what the data about

are the numbers 0000, 2000. 4000. 6 (HK) or 8000. a change five hundred times faster than with

5 (Jor 2-kH / -frequency. In addition, for the refined control of the data exchange

Summary of the advantages of the invention of variable frequency oscillator 205 '(FIG. 13)

^ dct, the frequency of which is proportional to the size

of the Fchler signal LS can be.

First ensures Π6 circuit (Fig. 6), Dali i «The use of 9-Komplcmenls in the U. the /? C7 pulses are each at least one time period -7-, H- and 77 (-Vcparallel circuits leads im long. The pulses are generated as a result of the "coincidence being 1 bit earlier than the 4 MHz frequency CK and a tilting pulse is developed than would normally be the case at the frequency which would be either 2 kHz, 20 (1 kHz, 1 MHz, or the change of the 10 complement,
can be variable, depending on the mode of the system. It follows that the offset has the effect. surgery. The /? CT pulses are with the 4 MHz - that they represent a '-bit error of the part that is frequency synchronized regardless of the original is represented by the data represented by the initial or repetition frequency of the toggle - «- Coincidence-Aulspür-Krcis can be controlled. To frequency. In addition, circuit 116 ensures that, described as correcting the error, in the n-channel synchronization circuit, Ab-20 introduces an I-bit delay.
-cluding an R (I -pulse, so that the system , if an electronic control state auxiliary control (not after counting and a skipping of a coincident shown) avoids the / during a countdown counting. 25 circle mi: feedback is used n- two-country system commands the error signal from channel d _cr measuring device 11 an electronic (not because the coincidence impulses shown directly responsible) control circuit in such a way that this is very important for the generated data, up or down counts. A zero state that the pulses are precisely determined. 30 does not exist. A two-state type of the bc-Is here has also been shown, "that the minus coincidence- s chricbcncn Systems shows a 1-bit oscillation, signals ( TIi, H and TU) through the Vcrwcn- when the machine part (not shown) is at rest. Establishing the 9 Complementary Circle 3 Means / To Eliminate This Condition Is To Be Developed. In essence, this signal can use C'ne's three-state system instead of aiii in a much simpler way than comparatively with the two-state system. This made possible; On-use of the Zchn-complement approximation waits-. Down and stop or zero finds can be generated. However, when using the signal. With a suitable adjustment of the zero band, the 10 complement method. If both occur, namely a tremor-free visual display on the display plus and the minus coincidence at zero and thawing device 21 can be achieved. However, this has a send. Since the synchronization circuit 116 has approximated the above 40 in many cases a reduction in the exposed conditions / for obscuration and system sensitivity by zero. That counting down here has to fulfill. it would be impossible for the system described using a two-state circuit 116 to produce a meaningful conclusion to the approximation, but eliminates the visual tremors in ^ Cr pulses when simultaneous coordinates of the last significant digit,
zidcnzcn exist. "45 If the machine part (represented by reference - The function generator!" Generates pulses, the characters 12 in FIG. I and reference characters 215 in on the TU and 4 7 "17 coincidence as in FIG. W)) moves in a positive direction. Tens and ones plus and minus comparison - then the inner counter 4 receives the command to circle 3 (Fig. I) found, based. Because the radio counting up. When the machine motion generator stops 500 pulses generating a 50, the inner counter continues counting up to quarter of the cycle used to develop the signals to reduce the Fchler signal until the data used requires the combined error signal to be zero . The reversal of the ned 7 "i / -Koinzidenz only a count of five TU Fehlcrsignals causes the up-Abwarts Lcitung coincidences more than 500 t / -.. (A) -Koinzidcnzen for switching the down mode, this order-How 6, sounding prevents the next RCT pulse from reaching the KCT pulse by combining the timing signal in counters 4 and 20. Simultaneously (4 MHz) with any one of the number or the I-bit delay in the ■ »-η channel is generated in the toggle signal (2 kHz, 200 kHz, etc.) Since the n-channel transfers and causes a rise, RCr pulses directly control the rate at which data is increased by I. The data change vcranla.it with which the data change is therefore an ideal signal for phase reversal, with the same means created for setting the speed the upward-downward conduction from downward as a function of the system requirements is reversed. Then ern For example, a ftC7 pulse is blocked during the normal display phase, and now the 1-bit counter 4 and 20 will be synchronized with the machine delay from the / i-channel back to the I / i-channel blades the frequency 65 »criihrl. This causes the function generator 10 to be 2 kHz. However, if the machine movement to generate an i-Bii change of the data 111 exceeds one speed or frequency, opposite direction. Thereupon the 1 Vlilcrsignal reverses again to a loss of the data synchronization. and the process continues

Claims (12)

Patent claims: 1. Digitally working position measuring system with a position measuring device, consisting of two measuring parts movable relative to one another, of which the first is arranged on a first machine part and the second is arranged on a second machine part, the second measuring part having several zero positions arranged at the same distance from one another and the system comprises an internal counter, the digital content of which represents a coordinate of the first measuring part between two zero positions of the second measuring part, an external counter and a display device which, controlled by the external counter, displays the content of the external counter, and also a converter which has the converts digital content of the internal counter into analog signals for the position measuring device to generate _ao an error signal depending on the mutual adjustment of the two measuring parts and depending on the analog signals, and an internal logic control device is provided which converts the error signal in digit converts all pulses, characterized in that a first memory (22) is provided which stores a numerical signal which corresponds to the distance of the first measuring part (12) with respect to a measurement reference zero point, and a control unit (9, 24) during a feeds this signal to the external counter (20) in the first working phase and connects the converter (2, 3, 10) to the internal counter (4) and the external counter (20) during a second working phase, the digital pulses ( RCT, 178) increase or decrease the count values of the counters (4, 20) by a value which corresponds to the adjustment of the first and second measuring parts (12, 13) with respect to one another. 2. Measuring system according to claim 1, characterized in that a second memory (23) vur is seen, which stores a first numerical signal which indicates the position of the measurement reference zero point corresponds to an adjacent zero position, with the Control unit (9, 24) feeds this signal to the internal counter (4). 3. Measuring system according to claim 2, characterized in that the first and second memory (22, 23) retain their stored values in the event of operational interruptions and in the event of a new one Start of operation the stored signals are available for the counters. 4. Measuring system according to claim 2, characterized in that the control device (9, 24) during during the first working phase sets the internal counter (4) to a first count (e.g. 1230), that of the position of the first measuring part between adjacent zero positions of the second measuring part if the measurement reference zero point is related to one of the zero positions, and the Outer counter (20) sets to zero, then the content (1230) of inner counter (4) sets the error signal (£ 5) causes digital pulses to be generated for the inner and outer counters (4, 20), the counter content by an amount I equal to the difference (0330) between the first Counting (1230) and the coordinate (0900) of the first measuring part changed, with the change in the inner counter (4) the error signal until the end of the generation of the digital pulses decreased and the change in the content in the external counter (20) is a display which is equal to the complementary value of J. 5. Measuring system according to claim 4, characterized in that the control device (9, 24) has a program circuit in the form of a counter (134) which can be switched through a plurality of states, further gates (142, 144) are provided, which in Depending on one of these states , generate signals (CL _n , CL _x ) which serve to reset the inner counter (4) and the outer counter (20) to zero, another gate (145) ii. Depending on a second state, a signal (UD _x ) is generated which causes the outer counter (20) to count according to the stored value of the first memory (22), the inner counter (4) counting together with the outer counter (20) at the same time and wherein the internal counter (4) reaches a content which corresponds to the position of the first measuring part between adjacent zero positions of the second measuring part when the measurement reference zero point is related to one of the zero positions, the gate (144) depending on a third state Signal (CL _x ) generated, which only resets the outer counter (20), and further gates (166, 167), depending on a fourth state , generate signals (VID _n , UfD _x ) that the outer counter (20) for counting together with the internal counter (4), and the internal logic control device (4) generates a signal (ÄCr pulses) under the control of the error signal (Es) for the internal counter (4), this internal counter (4) counts on a signal which corresponds to the coordinate of the first measuring part and the content of the external counter (20) and the display device (21, 21 ') corresponds to the complementary value of 1. 6. Measuring system according to claim 1, characterized in that the position measuring device (H] generates an error signal (Es) which is dependent on a comparison of the relative adjustment with trigonometric input signals (5C) of the position measuring device (11), a generator (10 for generating the trigonometric signals ir dependent on the error signal (Ex) is provided, this error signal (Es) causing the internal counter (4) to deliver the trigonometric signals in a direction in which the error signal (E.?) is reduced essentially to NuI will. 7. Measuring system according to claim 6, characterized in that the frequency-generating center (1 or 205 ') are provided for generating different frequencies and that of the error signal (£ 5) controlled switching means (5, 7, 8) eim high frequency when a certain th value of the error signal (Es) is exceeded and a low Frequency when falling below the certain! Value of the error signal (Es) from the frequency generating means (1, 205 ') the inner counter (4) supplies. 8. Measuring system according to claim 6 and 7, dadurc characterized in that the polarity (*>) of the error signal changes from one state to the other when the size of the error signal (£ 5) is reduced and passes through zero, that a detector (18) for detecting the state change of the error signal. ^ s is provided and furthermore a blocking circuit (104, 106 to 109) holds the external counter (20) and the display device (21, 210) at a constant value after the detector (18) detects a change in the polarity (e) of the error signal has. 9. Measuring system according to claim 6 and 7, characterized in that a reference counter (2) is provided that counts cyclically through a counting area and cyclically step-by-step through the counting area is switched by a frequency generating means (1), a comparator (3) the count of the reference counter (2) with the count of the internal counter (4) and compares a first series of pulses generated and continued with the complementary value of the count of the internal counter (4) a second Impulsreil.e, if there is coincidence between the counts, that continues digital circuits (83 to 94, 83 'to 94) are provided that depend on the first as and second pulse train generate pulses whose pulse width is related to the count of the inner counter (4), a filter (17) filters these pulses and these filtered pulses switching means (18, 19, S, 10), which are tnionometric Generate signals whose amplitudes are proportional to a trigonometric function of the angle represented by the count of the inner counter (4). 10. Measuring system according to claim 1 or 8, characterized in that the position measuring device (U) generates an error signal (Es) as a function of the comparison of the relative adjustment of the two measuring parts with a trigonometric input signal (SC) , the latter being fed to this measuring device (11) is, this trigonometric signal is generated by a generator (10) as a function of the Fchkrsignal (Es) and the error signal (Es) causes the internal counter (4) to generate the trigonometric signal in a direction in which the error signal (Es) im is reduced substantially to zero. 11. Messsyslem according to claim 4, characterized in that a working phase switch (24) is provided which -bzw between an initial position and a recording. Aiizeigeststellung is switchable, a program control circuit in the form of a counter (134) is controlled by this switch (24) and can be switched through several states, the program control circuit (134) being reset when this switch (24) is moved into its starting position, the Program control circuit (134) is moved through some of the switching states when the switch (24) is in its initial position, the outer counter (20) and the display device (21, IV) having a count which corresponds to the value 1, the In contrast, the program control circuit (134) moves through the other switching states when this switch (24) S ¹ Ch is in the recording position, the outer counter (20) and the display device (21, 21 ') have a content which corresponds to a starting value N which is equal to the distance between the part start position (215) between two zero positions of the second measuring part and a NuJi reference position (214) , wherein in the reading or display position of the switch (24) a subsequent movement of the first measuring part (12) into a new position of the outer counter (20) and the display device (21,21) are caused to to display new position relative to the zero reference position (214). 12. Measuring system according to claim 11, characterized in that the inner counter (4) is reset to a digital value which corresponds to the dimension between adjacent zero positions of the second measuring part, the inner counter (4) has a lower capacity than the outer counter (20 ) that further, while the switch (24) is in its starting position, the inner counter (4) has a count which corresponds to a value Y , where Y is the part start position (215) between two adjacent zero positions represents, the outer counter (20) has a value corresponding to Λ during this time, furthermore in the reading position of the switch (24) the inner counter (4) also contains this value Y and at this time the outer counter (20) has a content accordingly has the value N.