GB1261638A - Improvements relating to pulse counters - Google Patents

Abstract

1,261,638. Dynamic counter read-out. SOLATRON ELECTRONIC GROUP Ltd. 26 Feb., 1970 [27 Feb., 1969], No. 10664/69. Headings G4A and G4H. Dynamic display of the contents of a counter comprising cascaded stages is effected by cycling all stages simultaneously between successive input pulses. A count impulse at 9 is subject to a short delay at 12a before application at 8 to binary-coded decimal counter comprising decades 5-7. The count impulse is applied after a longer delay at 12b to open a gate- 11 to a train of ten high frequency clock pulses which run all the decades simultaneously through one cycle at the same time as a reference decade 14. The reference decade, either directly or through a decoder 15, marks each of the cathodes of indicator tubes 17-19 sequentially. As each of the decades 5- 7 passes through 9 the related AND gates 23-25 close anode switches 20-22 so that the counts in 5-7 are displayed at 17-19. Continuous read-out may be provided (Fig. 2, not shown) by the clock source pulsing lead 13 alternately with strobing the count input.