GB1244363A - Transistor circuit for delaying analogue signals - Google Patents

Abstract

1,244,363. Analogue signal delay circuits. FERNSEH G.m.b.H. 19 Sept., 1968 [19 Sept., 1967; 18 Oct., 1967; 18 Nov., 1967], No. 57231/70. Heading H3U. An analogue signl is passed along a succession of charge storage devices by the cyclic operation of common emitter transistor stages coupling the storage devices. When the clock signal in Fig. 1 is positive, capacitor 312 charges to an extent determined by the value of the signal at the base of transistor 311. When the clock becomes negative a corresponding charge is passed via the opposite conductivity transistor 32 to capacitor 332. In this way the charge is passed along the succession of capacitors. Diodes 324 and 334 discharge the capacitors during the other half-cycle of the clock pulses. The output may be taken through a filter which removes the clock frequency. In Fig. 2 (not shown), the transistors are all of the same conductivity type and adjacent transistors receive clock pulses of opposite phase. In addition, clock pulses are applied to the emitters. Diodes (413, 423 &c.) prevent discharge of the capacitors through the collector base paths. In Fig. 3a (not shown), the capacitors are replaced by charge storage diodes. Out-of-phase clock pulses for the collectors may be provided by a changeover switch (Fig. 3, not shown) and the charge may be transferred between capacitors one at a time in reverse order instead of in groups of alternate transistors by a cycle of clock pulses derived from a counter or shift register (Fig. 6, not shown).