GB1131210A - Improvements in and relating to integrated circuit logic matrices - Google Patents

Improvements in and relating to integrated circuit logic matrices

Info

Publication number
GB1131210A
GB1131210A GB4199167A GB4199167A GB1131210A GB 1131210 A GB1131210 A GB 1131210A GB 4199167 A GB4199167 A GB 4199167A GB 4199167 A GB4199167 A GB 4199167A GB 1131210 A GB1131210 A GB 1131210A
Authority
GB
United Kingdom
Prior art keywords
elements
matrix
connections
transistor
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4199167A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of GB1131210A publication Critical patent/GB1131210A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

1,131,210. Integrated circuits. INTERNATIONAL STANDARD ELECTRIC CORP. 14 Sept., 1967 [16 Sept., 1966], No. 41991/67. Heading H1K. In an integrated circuit logic matrix of the type comprising a destructible coupling element, e.g. a fuse fs1-fs4, between each incoming conductor ce1, ce2 and each outgoing conductor cs1, cs2 to enable the matrix to be adapted to the performance of a desired logic function by selective destruction of the elements, the provi. sion of buffer elements such as amplifiers, inverters or impedance transformers between the outgoing conductors and the outlet connections cns1, cns2 of the matrix prevents direct electrical access to the coupling elements because of the danger of destroying the buffer elements. This difficulty is obviated according to the invention by connecting a switching element (a transistor T7, T8) in parallel with each buffer element (transistor T5 and resistors re1-re3 or transistor T6 and resistors re4-re6) so that when appropriate potentials are applied to current supply connections cna1-cna3 and to selected inlet connections cne1, cne2 and outlet connections cns1, cns2 a selected switching element shunts its associated buffer element and carries current to destroy a selected coupling element whereas when logic signals are applied to the inlet connections the switching elements are blocked and do not affect the operation of the circuit. The matrix is formed in a block of silicon, and aluminium is deposited on the surface of the block to form the incoming and outgoing conductors. The fuses consist of portions of the conductors having reduced cross-sections.
GB4199167A 1966-09-16 1967-09-14 Improvements in and relating to integrated circuit logic matrices Expired GB1131210A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR76597A FR1499444A (en) 1966-09-16 1966-09-16 Integrated logic circuit matrix

Publications (1)

Publication Number Publication Date
GB1131210A true GB1131210A (en) 1968-10-23

Family

ID=8617252

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4199167A Expired GB1131210A (en) 1966-09-16 1967-09-14 Improvements in and relating to integrated circuit logic matrices

Country Status (2)

Country Link
FR (1) FR1499444A (en)
GB (1) GB1131210A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668655A (en) * 1970-03-26 1972-06-06 Cogar Corp Write once/read only semiconductor memory array
US3720925A (en) * 1970-10-19 1973-03-13 Rca Corp Memory system using variable threshold transistors
US3721964A (en) * 1970-02-18 1973-03-20 Hewlett Packard Co Integrated circuit read only memory bit organized in coincident select structure
US4101974A (en) * 1975-12-31 1978-07-18 Motorola, Inc. Personalizable read-only memory
EP0008946A2 (en) * 1978-09-08 1980-03-19 Fujitsu Limited A semiconductor memory device
EP0010139A1 (en) * 1978-10-24 1980-04-30 International Business Machines Corporation Read only memory cell using FET transistors
US4432070A (en) * 1981-09-30 1984-02-14 Monolithic Memories, Incorporated High speed PROM device
WO1987001867A1 (en) * 1985-09-11 1987-03-26 Robert Bosch Gmbh Multi-cell transistor
US5045726A (en) * 1990-05-16 1991-09-03 North American Philips Corporation Low power programming circuit for user programmable digital logic array

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3721964A (en) * 1970-02-18 1973-03-20 Hewlett Packard Co Integrated circuit read only memory bit organized in coincident select structure
US3668655A (en) * 1970-03-26 1972-06-06 Cogar Corp Write once/read only semiconductor memory array
US3720925A (en) * 1970-10-19 1973-03-13 Rca Corp Memory system using variable threshold transistors
US4101974A (en) * 1975-12-31 1978-07-18 Motorola, Inc. Personalizable read-only memory
EP0008946A2 (en) * 1978-09-08 1980-03-19 Fujitsu Limited A semiconductor memory device
EP0008946A3 (en) * 1978-09-08 1980-04-02 Fujitsu Limited A semiconductor memory device
EP0010139A1 (en) * 1978-10-24 1980-04-30 International Business Machines Corporation Read only memory cell using FET transistors
US4432070A (en) * 1981-09-30 1984-02-14 Monolithic Memories, Incorporated High speed PROM device
WO1987001867A1 (en) * 1985-09-11 1987-03-26 Robert Bosch Gmbh Multi-cell transistor
US5045726A (en) * 1990-05-16 1991-09-03 North American Philips Corporation Low power programming circuit for user programmable digital logic array

Also Published As

Publication number Publication date
FR1499444A (en) 1967-10-27

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