FR3102625B1 - Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant. - Google Patents

Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant. Download PDF

Info

Publication number
FR3102625B1
FR3102625B1 FR1912076A FR1912076A FR3102625B1 FR 3102625 B1 FR3102625 B1 FR 3102625B1 FR 1912076 A FR1912076 A FR 1912076A FR 1912076 A FR1912076 A FR 1912076A FR 3102625 B1 FR3102625 B1 FR 3102625B1
Authority
FR
France
Prior art keywords
control signal
locked loop
card mode
digital phase
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1912076A
Other languages
English (en)
Other versions
FR3102625A1 (fr
Inventor
Marc Houdebine
Laurent Garcia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR1912076A priority Critical patent/FR3102625B1/fr
Priority to US17/080,431 priority patent/US11190236B2/en
Priority to CN202022437095.7U priority patent/CN214412704U/zh
Priority to CN202011171709.XA priority patent/CN112737580A/zh
Publication of FR3102625A1 publication Critical patent/FR3102625A1/fr
Application granted granted Critical
Publication of FR3102625B1 publication Critical patent/FR3102625B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H04B5/72—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H04B5/22—
    • H04B5/70—
    • H04B5/77—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Le dispositif de communication en champ proche « NFC » par modulation active de charge, émulé en mode carte (DIS) et destiné à communiquer avec un lecteur (RD), comprend une boucle à verrouillage de phase (DPLL) numérique configurée pour générer un signal de porteuse (SP), comportant un oscillateur (VCO) configuré pour générer le signal de porteuse (SP) de façon commandée par un signal de commande analogique (VTUNE), un circuit de rétroaction (Rtr) configuré pour générer un signal de commande numérique (DAC_CTRL), un convertisseur numérique-analogique (DAC) configuré pour convertir le signal de commande numérique (DAC_CTRL) en ledit signal de commande analogique (VTUNE), et un montage intégrateur (INTG) configuré pour intégrer le signal de commande analogique (VTUNE). Figure de l’abrégé : figure 2
FR1912076A 2019-10-28 2019-10-28 Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant. Active FR3102625B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1912076A FR3102625B1 (fr) 2019-10-28 2019-10-28 Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant.
US17/080,431 US11190236B2 (en) 2019-10-28 2020-10-26 NFC device emulated in card mode comprising a digital phase locked loop, and corresponding communication method
CN202022437095.7U CN214412704U (zh) 2019-10-28 2020-10-28 使用有源负载调制的近场通信nfc设备
CN202011171709.XA CN112737580A (zh) 2019-10-28 2020-10-28 包括数字锁相环的卡模式仿真的nfc设备及相应通信方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1912076A FR3102625B1 (fr) 2019-10-28 2019-10-28 Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant.
FR1912076 2019-10-28

Publications (2)

Publication Number Publication Date
FR3102625A1 FR3102625A1 (fr) 2021-04-30
FR3102625B1 true FR3102625B1 (fr) 2021-11-12

Family

ID=69572129

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1912076A Active FR3102625B1 (fr) 2019-10-28 2019-10-28 Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant.

Country Status (3)

Country Link
US (1) US11190236B2 (fr)
CN (2) CN214412704U (fr)
FR (1) FR3102625B1 (fr)

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2825045B2 (ja) * 1992-08-05 1998-11-18 日本電気株式会社 周波数シンセサイザ
KR100547831B1 (ko) * 2003-06-18 2006-01-31 삼성전자주식회사 가변 데이터 전송률에 대응이 가능한 클럭 및 데이터 복원장치
US7224951B1 (en) * 2003-09-11 2007-05-29 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
GB2463879A (en) * 2008-09-25 2010-03-31 Ubidyne Inc Apparatus and method for the calibration of delta-sigma modulators of the continuous time, band pass, type.
GB2469473A (en) * 2009-04-14 2010-10-20 Cambridge Silicon Radio Ltd Digital phase locked loop
US8934836B2 (en) * 2012-06-28 2015-01-13 Broadcom Corporation NFC device with PLL controlled active load modulation
US10020931B2 (en) * 2013-03-07 2018-07-10 Intel Corporation Apparatus for dynamically adapting a clock generator with respect to changes in power supply
CN103269220A (zh) * 2013-05-30 2013-08-28 上海坤锐电子科技有限公司 基于数字琐相环的nfc有源负载调制的时钟恢复电路
US9014323B2 (en) * 2013-08-30 2015-04-21 Nxp B.V. Clock synchronizer for aligning remote devices
EP2988427B1 (fr) * 2014-08-22 2019-04-24 STMicroelectronics International N.V. Procédé d'étalonnage de phase dans un circuit de pré-amplification d'une communication en champ proche, NFC, dispositif étiquette, circuit de pré-amplification et dispositif d'étiquette NFC
EP3076552B1 (fr) * 2015-03-30 2019-01-30 Nxp B.V. Synchroniseur numérique
US9525576B1 (en) * 2015-07-24 2016-12-20 Seagate Technology Llc Self-adapting phase-locked loop filter for use in a read channel
US9742443B2 (en) * 2015-09-08 2017-08-22 Nxp B.V. Pulse shaping for radio frequency transmitters
US9929779B2 (en) * 2015-12-01 2018-03-27 Maxim Integrated Products, Inc. Power adaptive dual mode card emulation system for NFC and RFID application
SG10201509972YA (en) * 2015-12-04 2016-09-29 Huawei Internat Pte Ltd Asynchronous transmission for nfc card emulation mode
US10396975B2 (en) * 2016-06-29 2019-08-27 Maxim Integrated Products, Inc. Clock recovery system and method for near field communication with active load modulation
FR3054760A1 (fr) * 2016-07-27 2018-02-02 Stmicroelectronics Sa Procede de communication sans contact entre un objet, par exemple un telephone mobile emule en mode carte, et un lecteur par modulation active de charge
SG10201608437WA (en) * 2016-10-07 2018-05-30 Huawei Int Pte Ltd Active load modulation technique in near field communication
US9979404B1 (en) * 2016-12-30 2018-05-22 Silicon Laboratories Inc. Multi-phase amplitude and phase modulation
US10447350B2 (en) * 2017-01-11 2019-10-15 Mediatek Singapore Pte. Ltd. High-speed circuits for active load modulation and related methods
EP3429087B1 (fr) * 2017-07-12 2021-08-25 STMicroelectronics razvoj polprevodnikov d.o.o. Procede de synchronisation d'une horloge de modulation de charge active dans un transpondeur et transpondeur correspondant
KR102403623B1 (ko) * 2017-08-18 2022-05-30 삼성전자주식회사 클록 신호들 사이의 스큐를 조절하도록 구성되는 전자 회로
FR3077174B1 (fr) 2018-01-19 2021-04-09 St Microelectronics Sa Synchronisation entre un lecteur et un objet communiquant sans contact avec le lecteur par modulation active de charge
US10122527B1 (en) * 2018-03-23 2018-11-06 Northrop Grumman Systems Corporation Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop
FR3086476B1 (fr) 2018-09-25 2020-09-11 St Microelectronics Sa Synchronisation rapide entre un objet et un lecteur communiquant sans contact par une modulation active de charge
US10574303B1 (en) * 2018-12-28 2020-02-25 Nxp B.V. System and method to test and calibrate card-detection using active tag emulation

Also Published As

Publication number Publication date
CN112737580A (zh) 2021-04-30
US11190236B2 (en) 2021-11-30
US20210126672A1 (en) 2021-04-29
CN214412704U (zh) 2021-10-15
FR3102625A1 (fr) 2021-04-30

Similar Documents

Publication Publication Date Title
US10680586B2 (en) Spread spectrum clock generation apparatus and method, and display device and touch display device
KR20190083958A (ko) 위상 동기 루프에 대한 고속 컨버징 이득 교정을 수행하는 전자 회로 및 동작 방법
CN103563285B (zh) 用于同步第一时钟域与第二时钟域之间的数据移交的设备及方法
US10615953B2 (en) Apparatuses and methods for compensating phase fluctuations
US9973196B2 (en) Clock synchronizer
US9048851B2 (en) Spread-spectrum apparatus for voltage regulator
US11728817B2 (en) Clock and data recovery devices with fractional-N PLL
CN102801385A (zh) 集成电路装置、电子装置与补偿可控制振荡器频移的方法
CN102804606A (zh) 数字锁相环结构
KR102661125B1 (ko) 미세 타이밍 해상도를 갖는 무선 전력 송신
US7203262B2 (en) Methods and apparatus for signal modification in a fractional-N phase locked loop system
US20200177194A1 (en) Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock
FR3102625B1 (fr) Dispositif NFC émulé en mode carte comprenant une boucle à verrouillage de phase numérique, et procédé de communication correspondant.
CN102281059B (zh) 用于在分数-n型锁相环中量化降噪的方法和设备
WO2013048478A1 (fr) Appareil et procédé d'exécution de contrôle d'horloge à spectre étalé
JP2008515344A (ja) シグマデルタベースのフェーズロックループ
US20190089520A1 (en) System and method for controlling the impact of periodic jitter caused by non-ideal phase interpolators
US4503405A (en) Frequency modulation using a phase modulator
US11075784B1 (en) Wideband multiphase transmitter with two-point modulation
CN116224747A (zh) 基于自参考延迟单元的时间数字转换器
Han et al. All‐digital PLL with ΔΣ DLL embedded TDC
US7933358B2 (en) GFSK/FSK modulation circuit and related method implemented in a digital manner
Li et al. A 5.8 GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution
US8422536B2 (en) Spread spectrum clock signal generator method and system
Ko et al. Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20210430

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5