FR3089680B1 - Mémoire à lecture unique - Google Patents

Mémoire à lecture unique Download PDF

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Publication number
FR3089680B1
FR3089680B1 FR1872646A FR1872646A FR3089680B1 FR 3089680 B1 FR3089680 B1 FR 3089680B1 FR 1872646 A FR1872646 A FR 1872646A FR 1872646 A FR1872646 A FR 1872646A FR 3089680 B1 FR3089680 B1 FR 3089680B1
Authority
FR
France
Prior art keywords
flop
flip
read
output
once memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1872646A
Other languages
English (en)
Other versions
FR3089680A1 (fr
Inventor
Michael Peeters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proton World International NV
Original Assignee
Proton World International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proton World International NV filed Critical Proton World International NV
Priority to FR1872646A priority Critical patent/FR3089680B1/fr
Priority to US16/708,313 priority patent/US11200936B2/en
Publication of FR3089680A1 publication Critical patent/FR3089680A1/fr
Application granted granted Critical
Publication of FR3089680B1 publication Critical patent/FR3089680B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Mémoire à lecture unique La présente description concerne un circuit de mémoire volatile (3) comportant : au moins une première bascule (32) ; au moins une deuxième bascule (34) dont une entrée de mise à un (S2) est reliée à une sortie (Q1) de la première bascule ; et une première fonction logique (38) combinant au moins une sortie (Q2) de la deuxième bascule et une information représentative de la sortie (Q1) de la première bascule. Figure pour l'abrégé : Fig. 2
FR1872646A 2018-12-10 2018-12-10 Mémoire à lecture unique Active FR3089680B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1872646A FR3089680B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique
US16/708,313 US11200936B2 (en) 2018-12-10 2019-12-09 Read-once memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1872646A FR3089680B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique

Publications (2)

Publication Number Publication Date
FR3089680A1 FR3089680A1 (fr) 2020-06-12
FR3089680B1 true FR3089680B1 (fr) 2022-12-23

Family

ID=66641033

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1872646A Active FR3089680B1 (fr) 2018-12-10 2018-12-10 Mémoire à lecture unique

Country Status (2)

Country Link
US (1) US11200936B2 (fr)
FR (1) FR3089680B1 (fr)

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764986A (en) * 1972-08-09 1973-10-09 Mi2 Columbus Magnetic tape data processing system
JP3553786B2 (ja) * 1998-03-13 2004-08-11 松下電器産業株式会社 半導体集積回路装置およびその製造方法
FR2823364B1 (fr) * 2001-04-05 2003-06-27 St Microelectronics Sa Dispositif et procede de protection partielle en lecture d'une memoire non volatile
US7218567B1 (en) * 2005-09-23 2007-05-15 Xilinx, Inc. Method and apparatus for the protection of sensitive data within an integrated circuit
US9509313B2 (en) * 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
KR20110052941A (ko) * 2009-11-13 2011-05-19 삼성전자주식회사 어디티브 레이턴시를 가지는 반도체 장치
US8595575B2 (en) * 2010-12-30 2013-11-26 Hynix Semiconductor Inc. Semiconductor memory device, test circuit, and test operation method thereof
US8509003B2 (en) 2011-09-20 2013-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Read architecture for MRAM
JP2013122797A (ja) 2011-12-09 2013-06-20 Toshiba Corp 半導体記憶装置
US8717831B2 (en) * 2012-04-30 2014-05-06 Hewlett-Packard Development Company, L.P. Memory circuit
KR101991905B1 (ko) 2012-07-19 2019-06-24 삼성전자주식회사 불휘발성 메모리, 불휘발성 메모리의 읽기 방법 및 불휘발성 메모리를 포함하는 메모리 시스템
TW201417102A (zh) 2012-10-23 2014-05-01 Ind Tech Res Inst 電阻式記憶體裝置
US9230622B2 (en) * 2012-11-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous two/dual port access on 6T SRAM
US9558838B2 (en) * 2013-08-22 2017-01-31 Renesas Electronics Corporation Semiconductor device for masking data stored in twin cell and outputting masked data
US9262256B2 (en) * 2013-12-24 2016-02-16 Intel Corporation Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location
US10115467B2 (en) 2014-09-30 2018-10-30 Jonker Llc One time accessible (OTA) non-volatile memory
US10839086B2 (en) 2014-09-30 2020-11-17 Jonker Llc Method of operating ephemeral peripheral device
US9881687B2 (en) 2015-12-18 2018-01-30 Texas Instruments Incorporated Self-latch sense timing in a one-time-programmable memory architecture
US20170344295A1 (en) 2016-05-31 2017-11-30 Sandisk Technologies Llc System and method for fast secure destruction or erase of data in a non-volatile memory
KR102491358B1 (ko) 2016-11-22 2023-01-26 매그나칩 반도체 유한회사 센스 앰프 구동 장치
US10242747B1 (en) 2017-12-28 2019-03-26 Micron Technology, Inc. Charge loss failure mitigation

Also Published As

Publication number Publication date
US20200185018A1 (en) 2020-06-11
US11200936B2 (en) 2021-12-14
FR3089680A1 (fr) 2020-06-12

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