FR3106681B1 - Architecture neuromorphique - Google Patents
Architecture neuromorphique Download PDFInfo
- Publication number
- FR3106681B1 FR3106681B1 FR2000698A FR2000698A FR3106681B1 FR 3106681 B1 FR3106681 B1 FR 3106681B1 FR 2000698 A FR2000698 A FR 2000698A FR 2000698 A FR2000698 A FR 2000698A FR 3106681 B1 FR3106681 B1 FR 3106681B1
- Authority
- FR
- France
- Prior art keywords
- track
- routing circuit
- input
- routing
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013528 artificial neural network Methods 0.000 abstract 1
- 230000001537 neural effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Mathematical Physics (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Computer Hardware Design (AREA)
- Memory System (AREA)
- Logic Circuits (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Architecture neuromorphique La présente description concerne un circuit de routage pour router des signaux entre des circuits de neurones d’un réseau neuronal artificiel, le circuit de routage comprenant : une première cellule mémoire (302) ayant une entrée couplée à une première piste d’entrée (304) du circuit de routage et une sortie couplée à une première piste de colonne (308) ; une deuxième cellule mémoire (302) ayant une entrée couplée à une deuxième piste d’entrée (304) du circuit de routage et une sortie couplée à la première piste de colonne (308) ; et un premier circuit comparateur (310) agencé pour comparer un signal (IREAD1) présent sur la première piste de colonne (308) à un niveau de référence, et pour activer sélectivement un signal (VOUT1) sur une première piste de sortie (312) du circuit de routage en fonction de la comparaison. Figure pour l'abrégé : Fig. 3
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2000698A FR3106681B1 (fr) | 2020-01-24 | 2020-01-24 | Architecture neuromorphique |
EP21152919.3A EP3855366A1 (fr) | 2020-01-24 | 2021-01-22 | Architecture neuromorphique |
US17/248,373 US20210232905A1 (en) | 2020-01-24 | 2021-01-22 | Neuromorphic architecture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2000698 | 2020-01-24 | ||
FR2000698A FR3106681B1 (fr) | 2020-01-24 | 2020-01-24 | Architecture neuromorphique |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3106681A1 FR3106681A1 (fr) | 2021-07-30 |
FR3106681B1 true FR3106681B1 (fr) | 2022-05-06 |
Family
ID=70978056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR2000698A Active FR3106681B1 (fr) | 2020-01-24 | 2020-01-24 | Architecture neuromorphique |
Country Status (3)
Country | Link |
---|---|
US (1) | US20210232905A1 (fr) |
EP (1) | EP3855366A1 (fr) |
FR (1) | FR3106681B1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4174724B1 (fr) | 2021-10-26 | 2023-10-11 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Circuit de synapses d'inférence variationnelle |
FR3140974A1 (fr) * | 2022-10-14 | 2024-04-19 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Circuit neuromorphique |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8311965B2 (en) * | 2009-11-18 | 2012-11-13 | International Business Machines Corporation | Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material |
US11501143B2 (en) * | 2013-10-11 | 2022-11-15 | Hrl Laboratories, Llc | Scalable integrated circuit with synaptic electronics and CMOS integrated memristors |
US10169701B2 (en) * | 2015-05-26 | 2019-01-01 | International Business Machines Corporation | Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models |
JP6602279B2 (ja) * | 2016-09-20 | 2019-11-06 | 株式会社東芝 | メムキャパシタ、ニューロ素子およびニューラルネットワーク装置 |
US10824937B2 (en) * | 2016-12-20 | 2020-11-03 | Intel Corporation | Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory |
-
2020
- 2020-01-24 FR FR2000698A patent/FR3106681B1/fr active Active
-
2021
- 2021-01-22 US US17/248,373 patent/US20210232905A1/en active Pending
- 2021-01-22 EP EP21152919.3A patent/EP3855366A1/fr active Pending
Also Published As
Publication number | Publication date |
---|---|
FR3106681A1 (fr) | 2021-07-30 |
EP3855366A1 (fr) | 2021-07-28 |
US20210232905A1 (en) | 2021-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR3106681B1 (fr) | Architecture neuromorphique | |
Kramer | Compact integrated motion sensor with three-pixel interaction | |
US20040161123A1 (en) | Electronic device having sound output module | |
JP2019536389A (ja) | 時間依存ビジュアルデータを検出する画素回路 | |
US4618236A (en) | Focus detecting apparatus | |
CN100357823C (zh) | 焦点检测装置及其控制方法 | |
FR2699023A1 (fr) | Circuit à retard commandé. | |
US4562346A (en) | Apparatus and method for detecting focus condition of imaging optical system employing both sharpness detection and lateral shift detection | |
WO2021114886A1 (fr) | Procédé et dispositif d'acquisition d'image d'iris, et procédé et dispositif de mise au point | |
GB1576160A (en) | Focus detecting device prinicipally for a camera | |
US5148011A (en) | Distance measuring apparatus using integration of reflected light and obtaining a plurality of distance signals | |
US6710605B2 (en) | Method and apparatus for detecting valid signal information | |
KR100393022B1 (ko) | 연산회로, 연산장치, 그리고 반도체 연산회로 | |
JPS59107312A (ja) | 焦点検出信号処理方法 | |
JPH04349297A (ja) | センスアンプ回路 | |
JP2001255455A (ja) | 測距装置 | |
FR2382050A1 (fr) | Detecteur de zeros pour utilisation avec une memoire a tores | |
Thevaril et al. | Speech enhancement using adaptive neuro-fuzzy filtering | |
JPH0722924A (ja) | ピーク検出回路 | |
US5271059A (en) | Method and configuration for forming a line termination of a telephone line | |
Li et al. | A compact current mode neuron circuit with Gaussian taper learning capability | |
Philipp et al. | Single-chip stereo imager | |
CN114078484A (zh) | 语音情绪识别的方法、装置以及存储介质 | |
CN114783041B (zh) | 目标对象识别方法、电子设备和计算机可读存储介质 | |
JP2001108893A (ja) | 距離測定装置およびカメラ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20210730 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
PLFP | Fee payment |
Year of fee payment: 5 |