FR3074605B1 - Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe - Google Patents

Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe Download PDF

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Publication number
FR3074605B1
FR3074605B1 FR1761625A FR1761625A FR3074605B1 FR 3074605 B1 FR3074605 B1 FR 3074605B1 FR 1761625 A FR1761625 A FR 1761625A FR 1761625 A FR1761625 A FR 1761625A FR 3074605 B1 FR3074605 B1 FR 3074605B1
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FR
France
Prior art keywords
substrate
terminal
detecting
thinning
rear panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1761625A
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English (en)
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FR3074605A1 (fr
Inventor
Alexandre Sarafianos
Abderrezak Marzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
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STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1761625A priority Critical patent/FR3074605B1/fr
Priority to CN201811475025.1A priority patent/CN109946584B/zh
Priority to US16/209,044 priority patent/US10615086B2/en
Priority to CN201822024731.6U priority patent/CN209471957U/zh
Publication of FR3074605A1 publication Critical patent/FR3074605A1/fr
Application granted granted Critical
Publication of FR3074605B1 publication Critical patent/FR3074605B1/fr
Priority to US16/800,448 priority patent/US11562933B2/en
Priority to US18/082,155 priority patent/US20230119204A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Automation & Control Theory (AREA)
  • Ceramic Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Circuit intégré comportant un substrat semi-conducteur (S), réalisé au dessus d'une couche semi-conductrice enterrée (1) et comportant au moins un dispositif (DIS) de détection d'un amincissement éventuel du substrat (S) par sa face arrière (Fr) comportant un tampon non-inverseur (TNI) comportant une borne d'entrée (BE) et une borne de sortie (BS) et alimenté entre une borne d'alimentation (BV) et une borne de référence (BR), la couche semiconductrice enterrée (1) comportant la borne d'alimentation (BV), des moyens de contrôle (CTRL) configurés pour, dans une première configuration du tampon non inverseur (TNI), délivrer un signal d'entrée (SE) dans un premier état à la borne d'entrée (BE), et pour générer un premier signal de contrôle correspondant à une détection d'un amincissement du substrat (S) si le signal délivré par la borne de sortie (BS) est dans un deuxième état différent du premier état.
FR1761625A 2017-12-05 2017-12-05 Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe Active FR3074605B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR1761625A FR3074605B1 (fr) 2017-12-05 2017-12-05 Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe
CN201811475025.1A CN109946584B (zh) 2017-12-05 2018-12-04 检测集成电路的衬底经由其背面的可能减薄的方法、以及相关联的器件
US16/209,044 US10615086B2 (en) 2017-12-05 2018-12-04 Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device
CN201822024731.6U CN209471957U (zh) 2017-12-05 2018-12-04 一种集成电路
US16/800,448 US11562933B2 (en) 2017-12-05 2020-02-25 Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device
US18/082,155 US20230119204A1 (en) 2017-12-05 2022-12-15 Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1761625A FR3074605B1 (fr) 2017-12-05 2017-12-05 Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe
FR1761625 2017-12-05

Publications (2)

Publication Number Publication Date
FR3074605A1 FR3074605A1 (fr) 2019-06-07
FR3074605B1 true FR3074605B1 (fr) 2020-01-17

Family

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Application Number Title Priority Date Filing Date
FR1761625A Active FR3074605B1 (fr) 2017-12-05 2017-12-05 Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe

Country Status (3)

Country Link
US (3) US10615086B2 (fr)
CN (2) CN209471957U (fr)
FR (1) FR3074605B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3072211B1 (fr) * 2017-10-11 2021-12-10 St Microelectronics Rousset Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe
FR3074605B1 (fr) 2017-12-05 2020-01-17 Stmicroelectronics (Rousset) Sas Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI221645B (en) * 2001-01-19 2004-10-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
JP4785271B2 (ja) * 2001-04-27 2011-10-05 株式会社半導体エネルギー研究所 液晶表示装置、電子機器
KR100450683B1 (ko) * 2002-09-04 2004-10-01 삼성전자주식회사 Ｓｏｉ 기판에 형성되는 에스램 디바이스
JP2005134459A (ja) * 2003-10-28 2005-05-26 Seiko Epson Corp Ｔｆｔアレイ基板、電気光学装置、およびそれを用いた電子機器
US7309900B2 (en) * 2004-03-23 2007-12-18 Advanced Lcd Technologies Development Center Co., Ltd. Thin-film transistor formed on insulating substrate
EP1691413A1 (fr) * 2005-02-11 2006-08-16 Axalto SA Composant électronique protégé contre les attaques.
FR2981783B1 (fr) * 2011-10-19 2014-05-09 St Microelectronics Rousset Systeme de detection d'une attaque par laser d'une puce de circuit integre
US8748258B2 (en) * 2011-12-12 2014-06-10 International Business Machines Corporation Method and structure for forming on-chip high quality capacitors with ETSOI transistors
FR2986356B1 (fr) * 2012-01-27 2014-02-28 St Microelectronics Rousset Dispositif de protection d'un circuit integre contre des attaques en face arriere
JP6024354B2 (ja) * 2012-10-02 2016-11-16 富士通セミコンダクター株式会社 半導体集積回路装置及びその製造方法
CN104241357A (zh) * 2013-06-18 2014-12-24 中芯国际集成电路制造(上海)有限公司 一种晶体管、集成电路以及集成电路的制造方法
US9070683B2 (en) * 2013-06-20 2015-06-30 Freescale Semiconductor, Inc. Die fracture detection and humidity protection with double guard ring arrangement
US9768128B2 (en) * 2014-01-29 2017-09-19 Infineon Technologies Ag Chip and method for detecting an attack on a chip
FR3029343B1 (fr) * 2014-11-27 2018-03-30 Stmicroelectronics (Rousset) Sas Dispositif compact de memoire de type electriquement effacable et programmable
FR3074605B1 (fr) * 2017-12-05 2020-01-17 Stmicroelectronics (Rousset) Sas Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe

Also Published As

Publication number Publication date
US20190172759A1 (en) 2019-06-06
US20200194318A1 (en) 2020-06-18
US11562933B2 (en) 2023-01-24
US20230119204A1 (en) 2023-04-20
CN109946584A (zh) 2019-06-28
CN209471957U (zh) 2019-10-08
FR3074605A1 (fr) 2019-06-07
CN109946584B (zh) 2021-07-06
US10615086B2 (en) 2020-04-07

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