FR3072211B1 - Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe - Google Patents

Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe Download PDF

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Publication number
FR3072211B1
FR3072211B1 FR1759519A FR1759519A FR3072211B1 FR 3072211 B1 FR3072211 B1 FR 3072211B1 FR 1759519 A FR1759519 A FR 1759519A FR 1759519 A FR1759519 A FR 1759519A FR 3072211 B1 FR3072211 B1 FR 3072211B1
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FR
France
Prior art keywords
integrated circuit
substrate
thinning
injection
faults
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1759519A
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English (en)
Other versions
FR3072211A1 (fr
Inventor
Alexandre Sarafianos
Abderrezak Marzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1759519A priority Critical patent/FR3072211B1/fr
Priority to US16/154,456 priority patent/US10892234B2/en
Priority to CN201811180294.5A priority patent/CN109659279B/zh
Priority to CN201821642927.5U priority patent/CN209045528U/zh
Publication of FR3072211A1 publication Critical patent/FR3072211A1/fr
Priority to US17/091,466 priority patent/US11942440B2/en
Application granted granted Critical
Publication of FR3072211B1 publication Critical patent/FR3072211B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/004—Countermeasures against attacks on cryptographic mechanisms for fault attacks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Circuit intégré, comprenant un substrat semi-conducteur (S) ayant une face arrière (Fr) et comportant au moins un premier caisson semi-conducteur (C1) comportant des composants et au moins un deuxième caisson semi-conducteur (C2) isolé du premier caisson semi-conducteur et du reste du substrat, le deuxième caisson semi-conducteur (C2) comportant un dispositif (DIS) de détection configurable et adapté pour, dans une première configuration, détecter un amincissement du substrat par sa face arrière (Fr), et dans une deuxième configuration, détecter une injection de faute dans le circuit intégré.
FR1759519A 2017-10-11 2017-10-11 Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe Active FR3072211B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1759519A FR3072211B1 (fr) 2017-10-11 2017-10-11 Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe
US16/154,456 US10892234B2 (en) 2017-10-11 2018-10-08 Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit
CN201811180294.5A CN109659279B (zh) 2017-10-11 2018-10-10 用于检测集成电路中的差分故障分析攻击和对衬底的减薄的方法以及相关集成电路
CN201821642927.5U CN209045528U (zh) 2017-10-11 2018-10-10 集成电路
US17/091,466 US11942440B2 (en) 2017-10-11 2020-11-06 Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1759519A FR3072211B1 (fr) 2017-10-11 2017-10-11 Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe
FR1759519 2017-10-11

Publications (2)

Publication Number Publication Date
FR3072211A1 FR3072211A1 (fr) 2019-04-12
FR3072211B1 true FR3072211B1 (fr) 2021-12-10

Family

ID=62017324

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1759519A Active FR3072211B1 (fr) 2017-10-11 2017-10-11 Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe

Country Status (3)

Country Link
US (2) US10892234B2 (fr)
CN (2) CN109659279B (fr)
FR (1) FR3072211B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3072211B1 (fr) * 2017-10-11 2021-12-10 St Microelectronics Rousset Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe
FR3077678B1 (fr) 2018-02-07 2022-10-21 St Microelectronics Rousset Procede de detection d'une atteinte a l'integrite d'un substrat semi-conducteur d'un circuit integre depuis sa face arriere, et dispositif correspondant
FR3096175B1 (fr) * 2019-05-13 2021-05-07 St Microelectronics Rousset Procédé de détection d’une atteinte éventuelle à l’intégrité d’un substrat semi-conducteur d’un circuit intégré depuis sa face arrière, et circuit intégré correspondant

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AUPO797897A0 (en) * 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Media device (ART18)
US6107107A (en) * 1998-03-31 2000-08-22 Advanced Micro Devices, Inc. Analyzing an electronic circuit formed upon a frontside surface of a semiconductor substrate by detecting radiation exiting a backside surface coated with an antireflective material
US7298159B1 (en) * 2005-07-07 2007-11-20 National Semiconductor Corporation Method of measuring the leakage current of a deep trench isolation structure
EP1977481B1 (fr) * 2006-01-24 2013-08-21 NDS Limited Protection contre l'attaque de puces
CN101617319B (zh) * 2007-02-20 2012-09-26 Nxp股份有限公司 具有背面破坏防护的半导体装置
FR2946775A1 (fr) * 2009-06-15 2010-12-17 St Microelectronics Rousset Dispositif de detection d'amincissement du substrat d'une puce de circuit integre
GB2479871A (en) * 2010-04-26 2011-11-02 David Coyne System for preventing side channel attacks on a synchronous logic device.
FR2976721B1 (fr) * 2011-06-17 2013-06-21 St Microelectronics Rousset Dispositif de detection d'une attaque dans une puce de circuit integre
FR2976722B1 (fr) * 2011-06-17 2013-11-29 St Microelectronics Rousset Dispositif de protection d'une puce de circuit integre contre des attaques
FR2991083A1 (fr) * 2012-05-24 2013-11-29 St Microelectronics Grenoble 2 Procede et dispositif de protection d'un circuit integre contre des attaques par sa face arriere
FR2998417A1 (fr) * 2012-11-16 2014-05-23 St Microelectronics Rousset Procede de realisation d'un element pointu de circuit integre, et circuit integre correspondant
FR2998419B1 (fr) * 2012-11-21 2015-01-16 St Microelectronics Rousset Protection d'un circuit integre contre des attaques
US9768128B2 (en) * 2014-01-29 2017-09-19 Infineon Technologies Ag Chip and method for detecting an attack on a chip
US9965652B2 (en) * 2014-08-06 2018-05-08 Maxim Integrated Products, Inc. Detecting and thwarting backside attacks on secured systems
FR3042891B1 (fr) * 2015-10-22 2018-03-23 Stmicroelectronics (Rousset) Sas Puce electronique securisee
DE102015118144B4 (de) * 2015-10-23 2017-06-29 Infineon Technologies Ag Halbleiterkomponente mit Laser-Fuse-Verbindung und Leckagedetektionsschaltung und Verfahren zum Testen von integrierten Laser-Fuse-Verbindungen
EP3217307B1 (fr) * 2016-02-22 2018-11-07 Eshard Procédé d'essai de résistance d'un circuit à une analyse de canal latéral de second ordre ou au-delà
FR3050317A1 (fr) * 2016-04-19 2017-10-20 Stmicroelectronics Rousset Puce electronique
US20180089426A1 (en) * 2016-09-29 2018-03-29 Government Of The United States As Represented By The Secretary Of The Air Force System, method, and apparatus for resisting hardware trojan induced leakage in combinational logics
FR3063385B1 (fr) * 2017-02-28 2019-04-26 Stmicroelectronics (Rousset) Sas Circuit integre avec detection d'amincissement par la face arriere et condensateurs de decouplage
FR3071100B1 (fr) * 2017-09-13 2021-12-10 St Microelectronics Rousset Procede de detection d'un amincissement d'un substrat de circuit integre par sa face arriere, et circuit integre correspondant
FR3072211B1 (fr) * 2017-10-11 2021-12-10 St Microelectronics Rousset Procede de detection d'une injection de fautes et d'un amincissement du substrat dans un circuit integre, et circuit integre associe
FR3074605B1 (fr) * 2017-12-05 2020-01-17 Stmicroelectronics (Rousset) Sas Procede de detection d'un amincissement eventuel d'un substrat d'un circuit integre par sa face arriere, et dispositif associe

Also Published As

Publication number Publication date
FR3072211A1 (fr) 2019-04-12
US20210057358A1 (en) 2021-02-25
CN209045528U (zh) 2019-06-28
CN109659279B (zh) 2023-09-08
US20190109100A1 (en) 2019-04-11
US11942440B2 (en) 2024-03-26
CN109659279A (zh) 2019-04-19
US10892234B2 (en) 2021-01-12

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