FR3017981B1 - Programmation d'une memoire eeprom - Google Patents

Programmation d'une memoire eeprom

Info

Publication number
FR3017981B1
FR3017981B1 FR1451599A FR1451599A FR3017981B1 FR 3017981 B1 FR3017981 B1 FR 3017981B1 FR 1451599 A FR1451599 A FR 1451599A FR 1451599 A FR1451599 A FR 1451599A FR 3017981 B1 FR3017981 B1 FR 3017981B1
Authority
FR
France
Prior art keywords
programming
eeprom memory
writing
voltage
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1451599A
Other languages
English (en)
Other versions
FR3017981A1 (fr
Inventor
Francois Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1451599A priority Critical patent/FR3017981B1/fr
Priority to US14/632,785 priority patent/US9312012B2/en
Publication of FR3017981A1 publication Critical patent/FR3017981A1/fr
Application granted granted Critical
Publication of FR3017981B1 publication Critical patent/FR3017981B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

L'invention concerne un procédé de programmation d'une mémoire EEPROM comportant : un premier mode (MODE1) dans lequel une écriture dans des cellules s'effectue sous une première tension (HT1) ; et un deuxième mode (MODE2) dans lequel l'écriture s'effectue sous une deuxième tension (HT2), inférieure à la première.
FR1451599A 2014-02-27 2014-02-27 Programmation d'une memoire eeprom Expired - Fee Related FR3017981B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1451599A FR3017981B1 (fr) 2014-02-27 2014-02-27 Programmation d'une memoire eeprom
US14/632,785 US9312012B2 (en) 2014-02-27 2015-02-26 EEPROM programming with first and second programming modes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1451599A FR3017981B1 (fr) 2014-02-27 2014-02-27 Programmation d'une memoire eeprom

Publications (2)

Publication Number Publication Date
FR3017981A1 FR3017981A1 (fr) 2015-08-28
FR3017981B1 true FR3017981B1 (fr) 2017-07-21

Family

ID=50424654

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1451599A Expired - Fee Related FR3017981B1 (fr) 2014-02-27 2014-02-27 Programmation d'une memoire eeprom

Country Status (2)

Country Link
US (1) US9312012B2 (fr)
FR (1) FR3017981B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10056140B2 (en) * 2014-01-30 2018-08-21 Hewlett Packard Enterprise Development Lp Memristor memory with volatile and non-volatile states

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3200012B2 (ja) * 1996-04-19 2001-08-20 株式会社東芝 記憶システム
US7149121B2 (en) * 2005-01-26 2006-12-12 Macronix International Co., Ltd. Method and apparatus for changing operating conditions of nonvolatile memory
KR101333503B1 (ko) * 2006-02-03 2013-11-28 삼성전자주식회사 프로그램 셀의 수에 따라 프로그램 전압을 조절하는 반도체메모리 장치 및 그것의 프로그램 방법
US7495966B2 (en) * 2006-05-01 2009-02-24 Micron Technology, Inc. Memory voltage cycle adjustment
US8374036B2 (en) * 2008-11-14 2013-02-12 Hynix Semiconductor Inc. Method of operating nonvolatile memory device
KR20100090541A (ko) * 2009-02-06 2010-08-16 삼성전자주식회사 비트라인 바이어싱 타임을 단축하는 비휘발성 메모리 장치 및 이를 포함하는 메모리 시스템
US8891308B1 (en) * 2013-09-11 2014-11-18 Sandisk Technologies Inc. Dynamic erase voltage step size selection for 3D non-volatile memory

Also Published As

Publication number Publication date
US9312012B2 (en) 2016-04-12
FR3017981A1 (fr) 2015-08-28
US20150243361A1 (en) 2015-08-27

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