FR2963849B1 - Procede de fabrication d'un circuit electrique et circuit obtenu - Google Patents

Procede de fabrication d'un circuit electrique et circuit obtenu Download PDF

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Publication number
FR2963849B1
FR2963849B1 FR1157179A FR1157179A FR2963849B1 FR 2963849 B1 FR2963849 B1 FR 2963849B1 FR 1157179 A FR1157179 A FR 1157179A FR 1157179 A FR1157179 A FR 1157179A FR 2963849 B1 FR2963849 B1 FR 2963849B1
Authority
FR
France
Prior art keywords
circuit
manufacturing
electric circuit
electric
circuit obtained
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1157179A
Other languages
English (en)
Other versions
FR2963849A1 (fr
Inventor
Juergen Butz
Axel Franke
Frieder Haag
Heribert Weber
Arnim Hoechst
Sonja Knies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of FR2963849A1 publication Critical patent/FR2963849A1/fr
Application granted granted Critical
Publication of FR2963849B1 publication Critical patent/FR2963849B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
FR1157179A 2010-08-10 2011-08-05 Procede de fabrication d'un circuit electrique et circuit obtenu Expired - Fee Related FR2963849B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010039156A DE102010039156A1 (de) 2010-08-10 2010-08-10 Verfahren zum Herstellen einer elektrischen Schaltung und elektrische Schaltung
DE102010039156.5 2010-08-10

Publications (2)

Publication Number Publication Date
FR2963849A1 FR2963849A1 (fr) 2012-02-17
FR2963849B1 true FR2963849B1 (fr) 2018-01-19

Family

ID=44898808

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1157179A Expired - Fee Related FR2963849B1 (fr) 2010-08-10 2011-08-05 Procede de fabrication d'un circuit electrique et circuit obtenu

Country Status (5)

Country Link
US (1) US20120038065A1 (fr)
CN (1) CN102376539B (fr)
DE (1) DE102010039156A1 (fr)
FR (1) FR2963849B1 (fr)
IT (1) ITMI20111486A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952489B2 (en) * 2012-10-09 2015-02-10 Infineon Technologies Ag Semiconductor package and method for fabricating the same
JP5987696B2 (ja) * 2013-01-09 2016-09-07 富士通株式会社 半導体装置の製造方法
TWI515843B (zh) * 2013-12-16 2016-01-01 南茂科技股份有限公司 晶片封裝結構
US20160240452A1 (en) * 2015-02-18 2016-08-18 Semiconductor Components Industries, Llc Semiconductor packages with sub-terminals and related methods
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure

Family Cites Families (28)

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Publication number Priority date Publication date Assignee Title
NL6714336A (fr) 1967-10-21 1969-04-23
TW262595B (fr) * 1993-11-17 1995-11-11 Ikeda Takeshi
WO1997030418A2 (fr) * 1996-02-12 1997-08-21 David Finn Procede et dispositif pour la connexion d'un conducteur electrique
US5717243A (en) * 1996-04-24 1998-02-10 Harris Corporation Integrated circuit with an improved inductor structure and method of fabrication
DE19632117C1 (de) * 1996-08-08 1997-12-18 Siemens Ag Datenträger zur kontaktlosen Übertragung von elektrischen Signalen
JPH10193849A (ja) * 1996-12-27 1998-07-28 Rohm Co Ltd 回路チップ搭載カードおよび回路チップモジュール
US5936299A (en) * 1997-03-13 1999-08-10 International Business Machines Corporation Substrate contact for integrated spiral inductors
JP2000332155A (ja) * 1999-03-12 2000-11-30 Sony Corp 半導体装置及びその製造方法
WO2001006558A1 (fr) * 1999-07-16 2001-01-25 Matsushita Electric Industrial Co., Ltd. Emballage de dispositifs a semi-conducteurs et leur procede de fabrication
US6686650B1 (en) * 1999-10-08 2004-02-03 Dai Nippon Printing Co., Ltd. Non-contact data carrier and IC chip
JP4776752B2 (ja) * 2000-04-19 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置
AU7457401A (en) * 2000-06-21 2002-01-02 Hitachi Maxell, Ltd. Semiconductor chip and semiconductor device using the semiconductor chip
AU2001293304A1 (en) * 2000-09-19 2002-04-02 Nanopierce Technologies, Inc. Method for assembling components and antennae in radio frequency identification devices
JP2002299523A (ja) * 2001-03-30 2002-10-11 Toshiba Corp 半導体パッケージ
TWI233172B (en) * 2003-04-02 2005-05-21 Siliconware Precision Industries Co Ltd Non-leaded semiconductor package and method of fabricating the same
TWI361479B (en) * 2003-08-28 2012-04-01 Gct Semiconductor Inc Integrated circuit package having inductance loop formed from a bridge interconnect
EP1803154B1 (fr) * 2004-09-09 2010-08-04 Semiconductor Energy Laboratory Co., Ltd. Puce sans fil
JP2006108496A (ja) * 2004-10-07 2006-04-20 Hitachi Maxell Ltd 半導体装置
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
US7932590B2 (en) * 2006-07-13 2011-04-26 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements
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JP5005427B2 (ja) * 2007-05-25 2012-08-22 日本メクトロン株式会社 多層プリント配線板の製造方法
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US7986023B2 (en) * 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
US7816792B2 (en) * 2007-09-14 2010-10-19 Infineon Technologies Ag Semiconductor device with conductive interconnect
US8164158B2 (en) * 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US8241952B2 (en) * 2010-02-25 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out level chip scale package

Also Published As

Publication number Publication date
ITMI20111486A1 (it) 2012-02-11
DE102010039156A1 (de) 2012-02-16
CN102376539A (zh) 2012-03-14
CN102376539B (zh) 2019-05-14
FR2963849A1 (fr) 2012-02-17
US20120038065A1 (en) 2012-02-16

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