FR2869426B1 - Procede et circuit de generation de signaux d'horloge pour la communication par un bus serie - Google Patents

Procede et circuit de generation de signaux d'horloge pour la communication par un bus serie

Info

Publication number
FR2869426B1
FR2869426B1 FR0502868A FR0502868A FR2869426B1 FR 2869426 B1 FR2869426 B1 FR 2869426B1 FR 0502868 A FR0502868 A FR 0502868A FR 0502868 A FR0502868 A FR 0502868A FR 2869426 B1 FR2869426 B1 FR 2869426B1
Authority
FR
France
Prior art keywords
circuit
serial bus
clock signals
bus communication
generating clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0502868A
Other languages
English (en)
Other versions
FR2869426A1 (fr
Inventor
Hyuk Jun Sung
Chan Yong Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2869426A1 publication Critical patent/FR2869426A1/fr
Application granted granted Critical
Publication of FR2869426B1 publication Critical patent/FR2869426B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
FR0502868A 2004-03-29 2005-03-23 Procede et circuit de generation de signaux d'horloge pour la communication par un bus serie Active FR2869426B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040021285A KR100990484B1 (ko) 2004-03-29 2004-03-29 직렬 버스 통신을 위한 송신 클럭 신호 발생기

Publications (2)

Publication Number Publication Date
FR2869426A1 FR2869426A1 (fr) 2005-10-28
FR2869426B1 true FR2869426B1 (fr) 2012-12-21

Family

ID=34991582

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0502868A Active FR2869426B1 (fr) 2004-03-29 2005-03-23 Procede et circuit de generation de signaux d'horloge pour la communication par un bus serie

Country Status (5)

Country Link
US (1) US7493510B2 (fr)
KR (1) KR100990484B1 (fr)
CN (1) CN100435064C (fr)
DE (1) DE102005015764B4 (fr)
FR (1) FR2869426B1 (fr)

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CN101253517A (zh) * 2005-09-02 2008-08-27 Nxp股份有限公司 具有射频接口的数据载体
EP1772794A1 (fr) * 2005-10-10 2007-04-11 Axalto S.A. Procédé et circuit de génération locale d'horloge et carte à puce l'incluant
US7809973B2 (en) * 2005-11-16 2010-10-05 Cypress Semiconductor Corporation Spread spectrum clock for USB
KR100849222B1 (ko) * 2006-04-10 2008-07-31 삼성전자주식회사 직렬 전송 방식에 사용되는 전송주파수 제어 방법, 이를기록한 기록매체 및 장치
US7852408B2 (en) * 2006-05-16 2010-12-14 Lsi Corporation Fractional phase-locked loop for generating high-definition and standard-definition reference clocks
US20080065927A1 (en) * 2006-09-11 2008-03-13 Jin-Xiao Wu Circuit for controlling operations of universal serial bus (usb) device
KR100819390B1 (ko) * 2006-09-21 2008-04-04 지씨티 세미컨덕터 인코포레이티드 2개의 위상 동기 루프를 사용한 주파수 합성기
KR100741470B1 (ko) * 2006-09-26 2007-07-20 삼성전자주식회사 유에스비 장치를 위한 클럭 발생기
ITMI20070997A1 (it) * 2007-05-17 2008-11-18 Incard Sa Ic card con clock a bassa precisione
KR101400695B1 (ko) 2007-08-14 2014-06-27 삼성전자주식회사 안정된 클럭 신호를 생성할 수 있는 클럭 신호 발생기,상기 클럭 신호 발생기를 구비하는 반도체 메모리 장치 및그 방법
KR101506337B1 (ko) * 2008-03-07 2015-03-26 삼성전자주식회사 스마트 카드 시스템 및 그 구동 방법
TW200947184A (en) * 2008-05-14 2009-11-16 Pixart Imaging Inc Method for automatically adjusting clock frequency and clock frequency adjustment circuit
US7917797B2 (en) * 2008-05-22 2011-03-29 Xilinx, Inc. Clock generation using a fractional phase detector
ES2370587T3 (es) * 2009-04-14 2011-12-20 Actaris Sas Transmisión bidireccional inalámbrica de señales de datos serie entre un equipo electrónico y un contador de energía.
TWI423007B (zh) * 2009-12-31 2014-01-11 Via Tech Inc 串列匯流排裝置以及其時脈差補償方法
US20110248755A1 (en) * 2010-04-08 2011-10-13 Hasenplaugh William C Cross-feedback phase-locked loop for distributed clocking systems
US8504767B2 (en) * 2010-04-20 2013-08-06 Taejin Info Tech Co., Ltd. Raid controlled semiconductor storage device
WO2013048525A1 (fr) * 2011-10-01 2013-04-04 Intel Corporation Diviseur de fréquence fractionnaire numérique
EP2613442B1 (fr) * 2012-01-06 2015-05-13 u-blox AG Procédé de détermination de terme de décalage pour un signal de synthétiseur PLLS à pas fractionnaire, un synthétiseur pour réaliser le procédé, dispositif de traitement de signal et un récepteur GNSS
CN102722218A (zh) * 2012-05-23 2012-10-10 常州芯奇微电子科技有限公司 Usb时钟电路
CN103684445B (zh) * 2012-09-11 2016-08-17 成都锐成芯微科技有限责任公司 多相位高分辨率锁相环
FR3005542A1 (fr) * 2013-05-07 2014-11-14 St Microelectronics Grenoble 2 Systeme d'acquisition d'image multi-capteur
US8838846B1 (en) * 2013-06-27 2014-09-16 Crystal Instruments Corporation Autonomous, multi-channel USB data acquisition transducers
CN103955256B (zh) * 2014-04-24 2017-04-12 华为技术有限公司 时钟频率调制的方法和时钟频率调制装置
CN105049039B (zh) * 2015-07-08 2017-12-01 中国电子科技集团公司第四十一研究所 一种用于杂散抑制的小数分频电路
KR102432496B1 (ko) * 2015-12-11 2022-08-12 삼성전자주식회사 반도체 장치
US9954705B2 (en) * 2015-12-28 2018-04-24 Texas Instruments Incorporated Phase noise improvement techniques for wideband fractional-N synthesizers
TWI599889B (zh) * 2017-03-14 2017-09-21 芯籟半導體股份有限公司 自動產生時脈的通用序列匯流排控制器及其使用方法
KR102376725B1 (ko) * 2017-11-08 2022-03-21 삼성전자 주식회사 Rf 칩을 연결하는 전송선로의 위상 측정 방법 및 이를 위한 장치
KR20200082918A (ko) * 2018-12-31 2020-07-08 에스케이하이닉스 주식회사 클럭 생성 회로 및 이를 포함하는 메모리 장치
US11264999B2 (en) 2020-03-12 2022-03-01 Raytheon Company High resolution counter using phased shifted clock

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FR2772535B1 (fr) * 1997-12-11 2000-12-15 Micropross Interface de communication avec une carte a puce synchrone et dispositif equipe d'une telle interface
US6434706B1 (en) * 1999-05-24 2002-08-13 Koninklijke Philips Electronics N.V. Clock system for multiple component system including module clocks for safety margin of data transfers among processing modules
US6487219B1 (en) * 1999-09-08 2002-11-26 Skyworks Solutions, Inc. Multi-band receiver having multi-slot capability
FR2803925B1 (fr) 2000-01-18 2002-03-15 St Microelectronics Sa Dispositif de regeneration d'une horloge a partir d'au moins deux bits de synchronisation
US6343364B1 (en) 2000-07-13 2002-01-29 Schlumberger Malco Inc. Method and device for local clock generation using universal serial bus downstream received signals DP and DM
DE10041772C2 (de) 2000-08-25 2002-07-11 Infineon Technologies Ag Taktgenerator, insbesondere für USB-Geräte
JP3624848B2 (ja) 2000-10-19 2005-03-02 セイコーエプソン株式会社 クロック生成回路、データ転送制御装置及び電子機器
JP3587162B2 (ja) * 2000-10-31 2004-11-10 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US20040114609A1 (en) * 2001-02-14 2004-06-17 Ian Swarbrick Interconnection system
US6621353B2 (en) * 2001-11-07 2003-09-16 International Business Machines Corporation Phase locked loop reconfiguration
JP4012032B2 (ja) * 2001-11-20 2007-11-21 キヤノン株式会社 データ通信装置

Also Published As

Publication number Publication date
KR100990484B1 (ko) 2010-10-29
DE102005015764B4 (de) 2009-12-03
US20050216780A1 (en) 2005-09-29
US7493510B2 (en) 2009-02-17
DE102005015764A1 (de) 2005-10-27
CN1677309A (zh) 2005-10-05
CN100435064C (zh) 2008-11-19
FR2869426A1 (fr) 2005-10-28
KR20050096030A (ko) 2005-10-05

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