FR2868601B1 - Tranche de semiconducteur et procede de fabrication de dispositif a semiconducteur utilisant celle-ci - Google Patents
Tranche de semiconducteur et procede de fabrication de dispositif a semiconducteur utilisant celle-ciInfo
- Publication number
- FR2868601B1 FR2868601B1 FR0503039A FR0503039A FR2868601B1 FR 2868601 B1 FR2868601 B1 FR 2868601B1 FR 0503039 A FR0503039 A FR 0503039A FR 0503039 A FR0503039 A FR 0503039A FR 2868601 B1 FR2868601 B1 FR 2868601B1
- Authority
- FR
- France
- Prior art keywords
- same
- semiconductor device
- semiconductor wafer
- manufacturing
- manufacturing semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004099876A JP2005283432A (ja) | 2004-03-30 | 2004-03-30 | 半導体ウエハおよびその半導体ウエハを用いた半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2868601A1 FR2868601A1 (fr) | 2005-10-07 |
FR2868601B1 true FR2868601B1 (fr) | 2008-06-06 |
Family
ID=34982663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0503039A Expired - Fee Related FR2868601B1 (fr) | 2004-03-30 | 2005-03-29 | Tranche de semiconducteur et procede de fabrication de dispositif a semiconducteur utilisant celle-ci |
Country Status (4)
Country | Link |
---|---|
US (1) | US7229858B2 (fr) |
JP (1) | JP2005283432A (fr) |
DE (1) | DE102005014156A1 (fr) |
FR (1) | FR2868601B1 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7579689B2 (en) * | 2006-01-31 | 2009-08-25 | Mediatek Inc. | Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package |
US8063480B2 (en) * | 2006-02-28 | 2011-11-22 | Canon Kabushiki Kaisha | Printed board and semiconductor integrated circuit |
CN102279356A (zh) * | 2010-06-08 | 2011-12-14 | 旺宏电子股份有限公司 | 集成电路测试方法 |
ITMI20111418A1 (it) | 2011-07-28 | 2013-01-29 | St Microelectronics Srl | Architettura di testing di circuiti integrati su un wafer |
JP6179158B2 (ja) * | 2013-03-27 | 2017-08-16 | 三菱電機株式会社 | トランジスタの製造方法、増幅器の製造方法 |
JP6299117B2 (ja) | 2013-08-30 | 2018-03-28 | 三菱電機株式会社 | 窒化物半導体デバイスの製造方法、バーンイン装置 |
JP6292104B2 (ja) * | 2014-11-17 | 2018-03-14 | 三菱電機株式会社 | 窒化物半導体装置の製造方法 |
US10375971B1 (en) * | 2018-10-17 | 2019-08-13 | Joseph Tyminski | Cutting board and storage assembly |
CN115856588B (zh) * | 2023-02-22 | 2023-08-04 | 长鑫存储技术有限公司 | 芯片测试板及测试方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5367208A (en) * | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5191224A (en) * | 1987-04-22 | 1993-03-02 | Hitachi, Ltd. | Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein |
JPH05136243A (ja) | 1991-11-12 | 1993-06-01 | Nippon Eng Kk | エージング等テスト用パターンを付加した半導体ウエハー |
US5442282A (en) * | 1992-07-02 | 1995-08-15 | Lsi Logic Corporation | Testing and exercising individual, unsingulated dies on a wafer |
US5390011A (en) * | 1993-05-27 | 1995-02-14 | Delphax Systems | Compact imaging roll printer |
US5619462A (en) * | 1995-07-31 | 1997-04-08 | Sgs-Thomson Microelectronics, Inc. | Fault detection for entire wafer stress test |
US5994912A (en) * | 1995-10-31 | 1999-11-30 | Texas Instruments Incorporated | Fault tolerant selection of die on wafer |
US6313658B1 (en) * | 1998-05-22 | 2001-11-06 | Micron Technology, Inc. | Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer |
US6590412B2 (en) * | 2001-06-26 | 2003-07-08 | Logicvision, Inc. | Circuit and method for detecting transient voltages on a dc power supply rail |
US6967348B2 (en) * | 2002-06-20 | 2005-11-22 | Micron Technology, Inc. | Signal sharing circuit with microelectric die isolation features |
-
2004
- 2004-03-30 JP JP2004099876A patent/JP2005283432A/ja active Pending
-
2005
- 2005-03-29 DE DE102005014156A patent/DE102005014156A1/de not_active Ceased
- 2005-03-29 FR FR0503039A patent/FR2868601B1/fr not_active Expired - Fee Related
- 2005-03-29 US US11/091,450 patent/US7229858B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2868601A1 (fr) | 2005-10-07 |
DE102005014156A1 (de) | 2005-10-20 |
US20050218923A1 (en) | 2005-10-06 |
US7229858B2 (en) | 2007-06-12 |
JP2005283432A (ja) | 2005-10-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20111130 |