FR2868600A1 - Procede de preparation de puces electroniques, et ensemble de puces en resultant - Google Patents

Procede de preparation de puces electroniques, et ensemble de puces en resultant

Info

Publication number
FR2868600A1
FR2868600A1 FR0403558A FR0403558A FR2868600A1 FR 2868600 A1 FR2868600 A1 FR 2868600A1 FR 0403558 A FR0403558 A FR 0403558A FR 0403558 A FR0403558 A FR 0403558A FR 2868600 A1 FR2868600 A1 FR 2868600A1
Authority
FR
France
Prior art keywords
test
chip
module
preparation
electronic chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR0403558A
Other languages
English (en)
Inventor
Philippe Planelle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0403558A priority Critical patent/FR2868600A1/fr
Priority to PCT/FR2005/000831 priority patent/WO2005101482A1/fr
Publication of FR2868600A1 publication Critical patent/FR2868600A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

L'invention concerne un procédé permettant d'une part de tester, au moyen de signaux de test (St), des puces électroniques (11 à 13) réalisées sur une même plaquette (100) de matériau semi-conducteur, et d'autre part de discriminer les puces opérationnelles des puces défaillantes.Selon l'invention, chaque puce de la plaquette est dotée d'un module de réception (2) de signaux transmis sans contact, d'un module d'autotest (3) relié au module de réception (2) de cette même puce (11 à 13), et d'un révélateur optique d'état (4) commandé par le module d'autotest, de sorte que les signaux de test (St) peuvent être adressés en parallèle à toutes les puces de la plaquette, et que chaque puce ayant passé le test avec succès est directement identifiée par un changement d'état optique du révélateur d'état (4) commandée par le module d'autotest de cette puce.
FR0403558A 2004-04-05 2004-04-05 Procede de preparation de puces electroniques, et ensemble de puces en resultant Pending FR2868600A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0403558A FR2868600A1 (fr) 2004-04-05 2004-04-05 Procede de preparation de puces electroniques, et ensemble de puces en resultant
PCT/FR2005/000831 WO2005101482A1 (fr) 2004-04-05 2005-04-05 Procede de preparation de puces electroniques, et ensemble de puces en resultant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0403558A FR2868600A1 (fr) 2004-04-05 2004-04-05 Procede de preparation de puces electroniques, et ensemble de puces en resultant

Publications (1)

Publication Number Publication Date
FR2868600A1 true FR2868600A1 (fr) 2005-10-07

Family

ID=34944634

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0403558A Pending FR2868600A1 (fr) 2004-04-05 2004-04-05 Procede de preparation de puces electroniques, et ensemble de puces en resultant

Country Status (2)

Country Link
FR (1) FR2868600A1 (fr)
WO (1) WO2005101482A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6164137A (ja) * 1984-09-05 1986-04-02 Sharp Corp 半導体装置
JPS63102332A (ja) * 1986-10-20 1988-05-07 Matsushita Electronics Corp 半導体装置の検査方法
JPH0290549A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体装置
US5248936A (en) * 1990-10-01 1993-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and a method of testing the same
WO1999032893A1 (fr) * 1997-12-22 1999-07-01 Conexant Systems, Inc. Dispositif d'essai sans fil pour microplaquette
US6211689B1 (en) * 1998-01-14 2001-04-03 Nec Corporation Method for testing semiconductor device and semiconductor device with transistor circuit for marking

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6164137A (ja) * 1984-09-05 1986-04-02 Sharp Corp 半導体装置
JPS63102332A (ja) * 1986-10-20 1988-05-07 Matsushita Electronics Corp 半導体装置の検査方法
JPH0290549A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体装置
US5248936A (en) * 1990-10-01 1993-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and a method of testing the same
WO1999032893A1 (fr) * 1997-12-22 1999-07-01 Conexant Systems, Inc. Dispositif d'essai sans fil pour microplaquette
US6211689B1 (en) * 1998-01-14 2001-04-03 Nec Corporation Method for testing semiconductor device and semiconductor device with transistor circuit for marking

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 228 (E - 426) 8 August 1986 (1986-08-08) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 342 (E - 658) 14 September 1988 (1988-09-14) *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 282 (E - 0942) 19 June 1990 (1990-06-19) *

Also Published As

Publication number Publication date
WO2005101482A1 (fr) 2005-10-27

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