WO1999032893A1 - Dispositif d'essai sans fil pour microplaquette - Google Patents

Dispositif d'essai sans fil pour microplaquette Download PDF

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Publication number
WO1999032893A1
WO1999032893A1 PCT/US1998/027341 US9827341W WO9932893A1 WO 1999032893 A1 WO1999032893 A1 WO 1999032893A1 US 9827341 W US9827341 W US 9827341W WO 9932893 A1 WO9932893 A1 WO 9932893A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
integrated circuit
die
circuit die
electromagnetic
Prior art date
Application number
PCT/US1998/027341
Other languages
English (en)
Inventor
Stanley A. White
Kenneth S. Walley
James W. Johnston
P. Michael Henderson
Warner B. Andrews, Jr.
Kelly H. Hale
Original Assignee
Conexant Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Publication of WO1999032893A1 publication Critical patent/WO1999032893A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/315—Contactless testing by inductive methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits

Definitions

  • the present invention relates to testing individual integrated circuit devices.
  • the present invention relates to testing individual die or chips when they are in wafer form, in bare die form, or in packaged device form.
  • Integrated circuit die and in particular semiconductor integrated circuit die, are manufactured by fabricating several individual die or chips on a wafer. After fabrication, the wafer is cut up, or diced, into the individual die.
  • the manufacturer may desire to test the individual die on the wafer. After testing, those die that the test had determined to be defective are then marked. After the wafer is cut into individual die, the marked (defective) die are discarded. Such testing at the wafer stage permits the manufacturer to discard defective die prior to incurring the expense of packaging such defective die.
  • the manufacturer may also want to test the individual die after the wafer has been cut into the individual die, but before the die are packaged. Such testing identifies defective die, which are then discarded. Die testing permits the manufacturer to discard die the test determines are defective prior to incurring the expense of packaging such defective die.
  • test probes typically the individual die are tested at the wafer or bare die stages by contacting the die with test probes.
  • a first test input probe contacts a test input contact pad fabricated on each die, activates the circuitry on the die, and executes a test of the chip by applying a particular test signal to the die.
  • a second probe contacts another test contact pad on the die to detect how the circuitry of the die responds to the test. Die failing the test are discarded.
  • the manufacturer may also be interested in testing the device after it has been packaged- Input and output pins are provided on the packaged device to permit test signals to be applied to the device, and for the response signals to be read from the device.
  • the packaged device may be placed in a test apparatus having receptacles or plug openings that correspond to the pins of the packaged device.
  • contact pads must be included in the die design to provide points on the die for the test probes to contact or for the test pins of the packaged device.
  • Such contact pads may serve no useful purpose after testing is completed.
  • those test contact pads continue to occupy space on the die.
  • Such test contact pads may displace pads that could be used for other purposes.
  • the space consumed by such test contact pads could be used to increase the space available on the die for functional die circuitry.
  • the space used for test contact pads could be used to reduce the size of the die, which would permit more die to be manufactured or fabricated on a wafer.
  • contact pads are typically placed around the perimeter of the die.
  • the circuit to be tested may be in a central part of the die.
  • a conductive path, or trace must be provided from the circuit to be tested to the corresponding contact pad(s).
  • Each such conductive trace in the circuitry on a die complicates the overall design of the die circuitry. If the need to connect internal test circuits to perimeter contact pads could be eliminated, the design of integrated circuits could be simplified.
  • a further issue is the significant risk of damaging the device in the testing process. Using test probes to contact the bare die (before packaging, in either wafer form, or in individual die form) carries the physical risk of damage from probe contact.
  • the present invention is a system and method for testing semiconductor integrated circuit die, and a semiconductor integrated circuit die for testing by that system.
  • the circuitry of the die is probed electromagnetically to identify defects in the fabrication of the die.
  • a test device includes a transmitter element to couple wirelessly one or more test patterns to a matching receiver in the die.
  • An electromagnetic transmitter or radiator on the die transmits or radiates response signals from the die.
  • the matching receiver in the test device receives the response signals.
  • the transmitters and matching receivers may be inductors.
  • the integrated circuit die incorporates a test circuit portion.
  • the test circuit portion includes an electromagnetic receiver for receiving wireless electromagnetic radiation.
  • the die test circuit portion additionally includes an electromagnetic radiating element for emitting or transmitting wireless electromagnetic radiation in response to the electromagnetic radiation signals received by the die electromagnetic receiver.
  • the test apparatus includes an electromagnetic transmitter for transmitting wireless electromagnetic radiation to the receiver of the integrated circuit die, and an electromagnetic receiver for receiving wireless electromagnetic radiation transmitted by the integrated circuit die-
  • the test apparatus extends along opposite sides of the die to be tested, so that the strength and specificity of the coupling between the test apparatus and the die being tested is increased.
  • wireless test signals are transmitted from a test device to a test circuit portion of the semiconductor integrated circuit die.
  • the die performs a test sequence, and transmits wireless response signals.
  • the test apparatus detects the response signals transmitted by the integrated circuit die.
  • Figure 1 illustrates a semiconductor wafer containing a plurality of individual die that may be tested in accordance with the present invention.
  • Figure 2 is a representation of a semiconductor integrated circuit die on the wafer shown in Figure 1.
  • Figure 3 is a cross-sectional view of the die of Figure 2, taken along the line 3-3 of Figure 2.
  • Figure 4 is a partial schematic diagram of a portion of the circuitry of the die of
  • Figure 5 is a diagram of the test apparatus incorporating an aspect of the present invention.
  • Figures 6a and 6b are schematic diagrams of oscillators that may be used in an embodiment of the present invention.
  • Figure 7 is a schematic diagram of a receiver that may be used in accordance with an embodiment of the present invention.
  • a particular individual die 22 is identified.
  • the die 22 is designed and fabricated in accordance with an aspect of the present invention, as described below.
  • all the die on a wafer are identical. Therefore, all the other die on the wafer 20 may be considered to be identical to the die 22, so the die 22 will be described herein as representative of the die on the wafer.
  • the wafer 20 may contain some partial die 24 at the edges of the wafer 20. Many techniques for fabricating such wafers are generally known and available in the semiconductor manufacturing arts.
  • the wafer 20 is "diced” into the individual die, such as the die 22.
  • the process of dicing semiconductor wafers into the individual die is well understood in the art. Lasers or mechanical saws are conventionally used to dice the wafer into its individual die. Each separate individual die 22 may then be packaged using any of the conventionally available packaging techniques.
  • the representative semiconductor integrated circuit die 22 incorporating an aspect of the present invention is shown in Figure 2 as it may appear before being packaged.
  • the die 22 includes a circuitry portion 30, which contains the operational circuitry of the die. Typically, the circuitry 30 occupies the central portion of the die 22. Contact pads 32 around the perimeter of the die 22 provide contact points between the circuitry 30 and other devices or elements. When the die 22 is packaged, the wires for the packaged device contact the contact pads 32 on the die. Conductive leads or traces 34 connect the appropriate portions of the circuitry 30 with the corresponding contact pads 32. These elements are common in the semiconductor integrated circuit industry, and are well understood.
  • the die 22 is substantially flat.
  • the cross-sectional view of Figure 3 shows that the die 22 has a substrate layer 40, and a circuit layer 42. Consistent with conventional semiconductor integrated circuit technologies, the circuit elements are formed in the circuit layer 42 of the die 22.
  • the die has a first, or upper, surface 46, and a second, or lower, surface 48.
  • the upper and lower surfaces 46, 48 are substantially flat, and are substantially parallel with one another. This structure is also common and well known in the semiconductor integrated circuit arts.
  • the circuitry 30 of the die 22 includes one or more test circuit portions 50 ( Figure 2).
  • the test circuit portion 50 may be placed wherever convenient on the die 22.
  • the test circuit portion will be a portion of the die circuitry 30.
  • the test circuit portion 50 includes a test circuit 52 (shown representatively in Figure 4) that is to be tested, a receiver element 54, and a transmitter or emitter element 56.
  • the test circuit portion receives wireless test signals at the receiver element 54.
  • the test signals activate the test circuit 52, and cause the test circuit to perform one or more test sequences.
  • the test circuit produces test response signals to the emitter element 56.
  • the emitter element 56 radiates or wirelessly transmits those response signals.
  • the test circuit 52 may be a regular part of the functioning die circuitry 30. or may be a special test circuit designed specifically for testing purposes. The details of the design of the test circuit depend on the specific function or attribute of the circuitry 30 that is to be tested.
  • the test circuit 52 is designed to receive an input test signal.
  • test circuit 52 If the test circuit 52 operates as designed, it produces a test output signal in response to the test input signal. If the test circuit does not produce the proper response signal, that is an indication that there is a defect in the integrated circuit device.
  • the test circuitry may be designed consistently with current integrated circuit design techniques. Those familiar with the design of integrated circuit devices will be familiar with different types of test circuits that may be designed in integrated circuits.
  • the test input signals for the test circuit 52 are received wirelessly at the receiver element 54.
  • the receiver element 54 is electrically connected to the test circuit 52 so that the receiver element 54 receives wireless electromagnetic test signals and applies the received signals to the test circuit 52 as input test signals.
  • the receiver element 54 in the illustrated embodiment is an inductor for receiving inductively coupled signals and conducting those received signals to the test circuit 52.
  • a capacitive element could be used to receive capacitively coupled signals.
  • more elaborate receivers such as a radio frequency (RF) receiver, or a coherent optical receiver may be used to wirelessly receive test signals for the test circuit 52.
  • RF radio frequency
  • the test circuit response signals generated by the test circuit 52 in response to the signals received at the receiver 54 are radiated or transmitted wirelessly from a radiator or transmitter element 56 connected to the test circuit 52.
  • the transmitter element 56 may also be an inductor for inductively coupling signals from the test circuit 52.
  • a capacitive element could be used to capacitively couple signals from the test circuit 52.
  • more elaborate transmitters such as a radio frequency (RF) transmitter, or a coherent optical transmitter may be used to radiate or emit response signal information from the test circuit 52.
  • RF radio frequency
  • the test apparatus constructed in accordance with an aspect of the present invention generates test signals and wirelessly transmits those test signals to the receiver element 54 of the test circuit portion 50 of the die 22.
  • An exemplary test apparatus 60 is shown in Figure 5.
  • the test apparatus 60 includes a test controller 80, test circuitry 70, a transmitter element 72, and a receiver element 74.
  • the test controller 80 generates test signals for testing the test circuit 52. Those test signals are communicated over the test device circuitry 70 to the test device transmitter 72.
  • the test device transmitter 72 is part of a first, or transmitting, segment 71 of the test system 60.
  • the transmitter 72 wirelessly transmits those test signals as electromagnetic energy to the test circuit portion 50 of the die 22.
  • the test circuit portion 50 of the die 22 performs a test sequence in response to the test signal, and emits or transmits a response signal.
  • the test response signal emitted by the test circuit portion is received in the test device by the test device receiver 74.
  • the received response signal is communicated from the receiver 74 over the test device circuitry 70 to the test controller 80.
  • the receiver 74 is part of the test device receiving segment 73 of the test system 60.
  • test circuitry 70 connecting the test controller 80 with the test device transmitter 72 and test device receiver 74 may be shared between the transmitting segment 71 and receiving segment 73.
  • the circuitry for the transmitting segment 71 may be separated from the circuitry for the receiving segment 73 of the test device.
  • the test apparatus 60 includes an opening 64 for receiving the semiconductor integrated circuit die 22 for testing.
  • a receptacle 62 holds the die to be tested 22 in the opening 64.
  • the receptacle 62 may be a tray that is shaped to receive the die to be tested. If the die is to be tested while in wafer form, the tray 62 is shaped to receive the wafer. If the die is to be tested as a bare die, after the wafer has been diced, the tray 62 is shaped to correspond with the die. If the die is to be tested in its packaged form, the tray 62 is shaped to receive the packaged device.
  • the tray 62 shown in Figure 5 is shaped to receive a single bare die 22.
  • the die 22 rests with its lower surface 48 ( Figure 3) on the surface of the tray 62.
  • the tray 62 may include a rim 66 around its perimeter to aid in proper placement of the die on the tray.
  • the rim 66 also aids in holding the die in place on the tray.
  • the tray 62 is designed so that the die may easily be placed into and removed from the tray with a minimum of handling, and a minimum possibility of damage. Those familiar with the handling of semiconductor integrated circuits and wafers of semiconductor integrated circuits will be familiar with several types of wafer and die handling techniques.
  • the tray 62 is movable relative to the opening 64 in the test apparatus 60.
  • the tray 62 may be moved into and out of the opening. This allows the tray 62 to carry the die 22 into the opening 64 so that the test circuit portion 50 on the die 22 is in proximity with the test device transmitter 72 and the test device receiver 74.
  • the tray may be moved first to place one of those test circuit portions in proximity to the test device transmitter and receiver 72, 74, and then the tray may be moved so that another of those test circuit portions is in close proximity with the test device transmitter and receiver 72, 74.
  • the tray carrying the wafer may be moved so that the test apparatus may successively test each die on the wafer.
  • the tray 62 carrying the wafer may be moved to successively bring each individual die 22 into proximity with the test device transmitter and receiver 72, 74, so that each die on the wafer may be excessively tested by the test device 60.
  • the tray 62 may be mounted on tracks (not shown).
  • the tracks may be placed along the bottom of the opening 64, and rollers or wheels (not shown) may be mounted on the underside of the tray 62.
  • the tray may also be mounted on an external arm 94 that moves the tray into or out of the opening 64.
  • the arm 94 may provide the tray with lateral movement in two dimensions. That two dimensional movement may be beneficial when more than one test circuit portion 50 in a single die are to be tested, or if the tray carries a wafer of multiple individual die, each of which has one or more test circuit portions. Movement of the arm 94 may be controlled by a controller 92.
  • the controller 92 may include one or more electric motors, gears, and other conventional components. Other types of movable mountings for the tray 62 will suggest themselves to those skilled in the art.
  • the test device transmitter 72 and the test device receiver 74 are on opposite sides of the opening 64.
  • the test device transmitter 72 is near the upper side of the opening 64, and the test device receiver 74 is near the lower side of the opening 64 Ideally, for maximum signal coupling (as will be apparent from the description below), the test device transmitter 72 is directly above the test device receiver 74.
  • the test device (including the tray 62) and the integrated circuit die 22 are designed to cooperate so that, during testing, the test circuit portion 50 is near the test device transmitter 72 and the test device receiver 74.
  • the tray 62 carries the die 22 into the opening 64 so that the test circuit portion 50 of the die is between the test device transmitter 72 and the test device receiver 74.
  • This placement provides for the test device transmitter 72 to be in close proximity to the receiver element 54 ( Figure 4) of the test circuit portion 50, and for the test device receiver 74 to be in close proximity to the emitter element 56 ( Figure 4) of the test circuit portion 50.
  • the test device transmitter 72 may wirelessly couple signals to the die receiver 54 to activate the test circuit 52 and execute tests in the test circuit 52.
  • the die emitter 56 may wirelessly couple signals such as test response signals to the test device receiver 74.
  • a moving electrical charge (a current) generates a magnetic field.
  • a moving magnetic field generates an electric field having a voltage, which can give rise to an electrical current. This pair of phenomena allows the electrical signals or the electrical effects in the test device transmitter 72 to be wirelessly communicated to the receiver 54 of the test circuit portion 50 of the die 22.
  • the die 22 is positioned within the opening 64 so that the test circuit portion 50 on the die is less than ten centimeters from the test device transmitter 72, and also less than ten centimeters from the test device receiver 74.
  • the test circuit portion 50 is placed within three centimeters of the test device transmitter 72, and also within three centimeters of the test device receiver 74.
  • Test patterns may be radiated by the transmitter element 72 of the test fixture circuitry directly to the die receiver element 54 in the test circuit portion 50 of the integrated circuit die 22.
  • Inductive coupling may be used for that purpose.
  • the test device transmitter 72 is an inductor
  • the receiver element 54 of the die test circuit portion 50 is also an inductor.
  • Capacitive coupling between a capacitive element as the test device transmitter 72 and a capacitive element as the receiver 54 of the die test circuit portion 50 may also be used.
  • the illustrated arrangement in which the transmitter 72 and the receiver 74 are directly above and below the test circuit portion 50, respectively, provides the highest degree of electromagnetic coupling.
  • a low reluctance flux return path 90 between a point near the test device transmitter 72 and test device receiver 74 improves the coupling from the test device and the specific test circuit portion of the die 22. So focusing the electromagnetic coupling reduces the likelihood that circuits on the die 22 other than the intended test circuit portion 50 are activated, and reduces the possibility of the test device receiver 74 detecting electromagnetic radiation emitted by other portions of the die 22.
  • the low reluctance flux return path 90 may be a strand of wire, or a rigid frame within the test device 60. The exact configuration that works best and provides the most effective trade-off between cost and performance may be determined by those skilled in the art for each application.
  • the test patterns may be encoded onto electromagnetic radiation that is wirelessly transmitted by the test device transmitter 72.
  • the test device transmitter 72 may include a transmitting oscillator circuit for modulating the information onto a radio-frequency (RF) carrier.
  • the test device transmitter 72 converts electrical signals on the test device circuitry 70 into electromagnetic radiation that corresponds to those signals.
  • the information of a first electrical signal generated by the test controller 80 may be modulated onto a radio frequency (RF) carrier wave generated by the transmitter 72.
  • the receiver element 54 of the die test circuit portion 50 in close proximity to the test device transmitter 72, detects the emitted radiation.
  • the receiver 54 detects the radio frequency signal, and demodulates it to recover the information from the signal for use by the test circuit 52.
  • the transmitter 72 modulates or encodes the signal onto an RF carrier.
  • the receiver 54 of the circuit portion 50 then demodulates or decodes the information from the RF signal.
  • Such encoding or modulation allows the receiver 54 of the test circuit portion 50 to distinguish the RF signals emanating from the test device transmitter 72, and to distinguish those signals from the background noise.
  • Simple modulation and demodulation schemes may be used for modulating test patterns onto electromagnetic carrier signals, such as RF signals. Such modulation maximizes the likelihood of a strong signal coupling between the radiating element and the receiving element.
  • An NPN Hartley oscillator as shown in Figure 6a may be used for modulation purposes.
  • an NPN Colpitts oscillator as shown in Figure 6b may be used.
  • the Hartley and Colpitts oscillators are well understood in the art.
  • the modulation may be amplitude modulation, frequency modulation, or spread spectrum encoding.
  • the oscillators shown in Figures 6a and 6b are most useful for amplitude modulation. Frequency modulation and spread spectrum signals may require more sophisticated implementations.
  • Useful instruction may be found in the McGraw-Hill Encyclopedia of Science and Technology, published by McGraw-Hill and Company, and in The Radio Amateur's Handbook, published by the American Radio Relay League. Those skilled in the art will also find information in The Electrical Engineering Handbook, (edited by R. C. Dorf, and published by the CRC Press), and in Reference Data for Engineers: Radio, Electronics, Computer, and Communications, (edited by E. C. Jordan and published by Howard W. Sams & Co.).
  • the die receiver element 54 ( Figure 4) is designed to receive and demodulate such RF signals.
  • An exemplary receiver that may be used in the die test circuit portion 50 is shown in Figure 7.
  • infrared radiation may be used to carry the information.
  • An infrared generator (not shown) in the transmitter 72 may be used to encode information onto an infrared beam.
  • Yet further embodiments may incorporate one or more lasers (not shown) to transmit information. The information is modulated or encoded onto a beam of coherent optical radiation (light) emitted by the laser.
  • a corresponding receiver is incorporated in the die test circuit portion 50 as the receiver 54.
  • test controller 80 The test patterns radiated by the test circuit radiating element 72 to the test circuit portion 50 of the integrated circuit die 22 are generated by the test controller 80.
  • the test controller 80 may include, for example, a programmed microprocessor 82 and one or more Random Access Memory devices 84. Those skilled in the art will also recognize how those patterns may be generated by the test controller 80.
  • Predetermined sets of codes may be stored in the RAM 84. These codes are designed to test a specific circuit. They include a predetermined test sequence, and a predetermined response sequence. When the test sequence is applied to the circuit under test, the circuit produces the known response sequence if the circuit is operating properly. Therefore, the test controller 80 compares the response sequence received from the circuit portion 50 with the expected response sequence. If the received response sequence does not match the stored, expected response sequence bit for bit, or character for character (depending on the level of the test), the circuit portion 50 is presumed defective. The microprocessor 82 in the test controller 80 tracks which test is run, and whether a defect has been detected.
  • the microprocessor 82 may also control the movement of the tray or receptacle 62 holding the die 22 by sending control signals to the controller 92 that directs the movement of the arm 94 holding the receptacle 62.
  • the controller 92 may include a microprocessor or another element to provide direction to the arm 94.
  • the response signals generated by the die test circuit 52 and emitted by the die emitter element 56 of the test circuit portion 50 of the integrated circuit die 22 may also be radiated or transmitted directly to the test device receiver 74, or may be modulated onto an electromagnetic carrier signal for radiation or transmission to the receiver 74 of the test fixture.
  • test circuit emitter 56 of the die test circuit portion 50 communicates to the test device receiver 74 in the same manner as a test device transmitter 72 communicates with the die test circuit receiver 54.
  • inductive coupling is used to communicate test signals from the test device transmitter 74 to the receiver 54 of the test circuit portion 50 of the die 22.
  • Inductive coupling is also used to transfer signals from the emitter element 56 of the test circuit portion 52 to the receiver 74 of the test device.
  • an oscillator such as one of the oscillators shown in the circuit diagrams of Figures 6a and 6b may be used.
  • the test device receiver 74 may include a receiver section similar to that shown in Figure 7. Again, these elements are well understood by those familiar with a wireless transmission of information.
  • test circuit portion 50 and the inductors 72, 74 shown in Figure 5 may all be associated with coupling the test signal to the semiconductor die 22.
  • a similar set of elements may be included in the test device 60 to receive the response signal from the die 22. Those elements may be displaced from the elements 72, 74 so that the receiving elements of the test device do not directly receive the test signal from the transmitting elements 72, 74.
  • the transmitter 72 of the test device may modulate the test signals onto a first carrier frequency
  • the transmitting section 54 ( Figure 4) of the test circuit portion 50 may modulate the response signals onto a second carrier frequency.
  • the test device transmitter 72 and the transmitting section 56 ( Figure 4) of the die test circuit portion 50 may modulate the test and response signals onto the same carrier frequency, but use mutually orthogonal modulation schemes.
  • the test device transmitter 72 uses a first modulation scheme
  • the transmitting section 56 ( Figure 4) of the test circuit portion 50 on the die 22 uses a second modulation scheme, wherein the first and second modulation schemes are mutually orthogonal.
  • the response receiver 74 of the test device does not "hear" the test device transmitter 72
  • the receiving section 54 of the test circuit portion 50 does not "hear" the transmitting section 56.
  • test circuit portions such as the test per circuit portion 50 shown in Figure 2 may be included on a particular semiconductor integrated circuit die 22.
  • Each such test circuit portion on the integrated circuit die is tested by a signal transmitted from a test device transmitter such as the transmitter 72.
  • the response wirelessly radiated by each such test circuit portion is received by a corresponding test device receiver such as the test device receiver 74.
  • Each test circuit portion 50 on the die may be individually activated by using modulation schemes with different carrier frequencies for the different test circuit portions.
  • a single pair of test device transmitting and receiving devices 72, 74 can be used to test multiple test circuit portions on the die 22, with the tray 62 moving the die 22 so that the different test circuit portions 50 are successively brought into proximity with the single pair of test device radiating and receiving elements 72, 74.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention se rapporte à une microplaquette comportant une partie de circuit d'essai comprenant un premier récepteur électromagnétique conçu pour recevoir sans fil un rayonnement électromagnétique, et un premier élément d'émission électromagnétique conçu pour émettre sans fil un rayonnement électromagnétique en réponse au rayonnement électromagnétique reçu par le premier récepteur électromagnétique. L'appareil d'essai de cette invention comporte un second émetteur électromagnétique conçu pour émettre sans fil un rayonnement électromagnétique à destination du premier récepteur de la microplaquette, et un second récepteur électromagnétique conçu pour recevoir sans fil un rayonnement électromagnétique émis par le premier émetteur de la microplaquette. Conformément au procédé de la présente invention qui permet de mettre à l'essai une microplaquette de semi-conducteurs, des signaux d'essai sont émis sans fil du dispositif d'essai à destination de la partie circuit d'essai de la microplaquette de semi-conducteurs. En réponse à ces signaux émis, la partie circuit d'essai de la microplaquette exécute une séquence d'essai et émet des signaux de réponse radioélectriques.
PCT/US1998/027341 1997-12-22 1998-12-21 Dispositif d'essai sans fil pour microplaquette WO1999032893A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99561997A 1997-12-22 1997-12-22
US08/995,619 1997-12-22

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WO1999032893A1 true WO1999032893A1 (fr) 1999-07-01

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000072030A1 (fr) * 1999-05-21 2000-11-30 Conexant Systems, Inc. Procede et appareil destines a tester sans fil des circuits integres
EP1143256A2 (fr) * 2000-04-05 2001-10-10 Infineon Technologies AG Dispositif de test pour le test fonctionnel d'un circuit semiconducteur
WO2001088976A2 (fr) * 2000-05-15 2001-11-22 The Governors Of The University Of Alberta Conception d'une technique radio frequence sans fil et procede d'essai de circuits integres et de plaquettes
US6331782B1 (en) 1998-03-23 2001-12-18 Conexant Systems, Inc. Method and apparatus for wireless testing of integrated circuits
US6647525B1 (en) * 1999-12-16 2003-11-11 Texas Instruments Incorporated Electronics testing circuit and method
EP1559216A2 (fr) * 2002-10-25 2005-08-03 Gennum Corporation - module de reception optique a couplage direct et procede de test
FR2868600A1 (fr) * 2004-04-05 2005-10-07 St Microelectronics Sa Procede de preparation de puces electroniques, et ensemble de puces en resultant
WO2005020297A3 (fr) * 2003-08-25 2006-04-13 Tau Metrix Inc Technique pour evaluer la fabrication d'une plaquette et d'un composant semi-conducteur
EP1754074A2 (fr) * 2004-02-05 2007-02-21 FormFactor, Inc. Interfa age exempt de contact de signaux d'essai avec un dispositif a l'essai
US7391005B2 (en) 2002-10-25 2008-06-24 Gennum Corporation Direct attach optical receiver module and method of testing
US7674635B2 (en) 2001-03-19 2010-03-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7902845B2 (en) 2001-03-19 2011-03-08 Semiconductor Energy Laboratory Co., Ltd. Inspection method and inspection apparatus
US8193827B2 (en) 2001-05-15 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Measuring method, inspection method, inspection device, semiconductor device, method of manufacturing a semiconductor device, and method of manufacturing an element substrate
CN110031744A (zh) * 2017-12-12 2019-07-19 美光科技公司 用于测试半导体裸片的测试探针设备及相关系统及方法

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US6331782B1 (en) 1998-03-23 2001-12-18 Conexant Systems, Inc. Method and apparatus for wireless testing of integrated circuits
WO2000072030A1 (fr) * 1999-05-21 2000-11-30 Conexant Systems, Inc. Procede et appareil destines a tester sans fil des circuits integres
US6647525B1 (en) * 1999-12-16 2003-11-11 Texas Instruments Incorporated Electronics testing circuit and method
EP1143256A3 (fr) * 2000-04-05 2003-11-12 Infineon Technologies AG Dispositif de test pour le test fonctionnel d'un circuit semiconducteur
EP1143256A2 (fr) * 2000-04-05 2001-10-10 Infineon Technologies AG Dispositif de test pour le test fonctionnel d'un circuit semiconducteur
US6825682B2 (en) 2000-04-05 2004-11-30 Infineon Technologies Ag Test configuration for the functional testing of a semiconductor chip
US8028208B2 (en) 2000-05-15 2011-09-27 Scanimetrics Inc. Wireless radio frequency technique design and method for testing of integrated circuits and wafers
US7183788B2 (en) 2000-05-15 2007-02-27 Scanimetrics Inc. Wireless radio frequency technique design and method for testing of integrated circuits and wafers
WO2001088976A3 (fr) * 2000-05-15 2002-07-18 Univ Alberta Conception d'une technique radio frequence sans fil et procede d'essai de circuits integres et de plaquettes
US6759863B2 (en) 2000-05-15 2004-07-06 The Governors Of The University Of Alberta Wireless radio frequency technique design and method for testing of integrated circuits and wafers
WO2001088976A2 (fr) * 2000-05-15 2001-11-22 The Governors Of The University Of Alberta Conception d'une technique radio frequence sans fil et procede d'essai de circuits integres et de plaquettes
US8664967B2 (en) 2001-03-19 2014-03-04 Semiconductor Energy Laboratory Co., Ltd. Inspection method and inspection apparatus
US7674635B2 (en) 2001-03-19 2010-03-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US9047796B2 (en) 2001-03-19 2015-06-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US8729548B2 (en) 2001-03-19 2014-05-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7902845B2 (en) 2001-03-19 2011-03-08 Semiconductor Energy Laboratory Co., Ltd. Inspection method and inspection apparatus
US8193827B2 (en) 2001-05-15 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Measuring method, inspection method, inspection device, semiconductor device, method of manufacturing a semiconductor device, and method of manufacturing an element substrate
EP1559216A2 (fr) * 2002-10-25 2005-08-03 Gennum Corporation - module de reception optique a couplage direct et procede de test
US7391005B2 (en) 2002-10-25 2008-06-24 Gennum Corporation Direct attach optical receiver module and method of testing
US7339388B2 (en) 2003-08-25 2008-03-04 Tau-Metrix, Inc. Intra-clip power and test signal generation for use with test structures on wafers
US8344745B2 (en) 2003-08-25 2013-01-01 Tau-Metrix, Inc. Test structures for evaluating a fabrication of a die or a wafer
US7736916B2 (en) 2003-08-25 2010-06-15 Tau-Metrix, Inc. System and apparatus for using test structures inside of a chip during the fabrication of the chip
WO2005020297A3 (fr) * 2003-08-25 2006-04-13 Tau Metrix Inc Technique pour evaluer la fabrication d'une plaquette et d'un composant semi-conducteur
US7723724B2 (en) 2003-08-25 2010-05-25 Tau-Metrix, Inc. System for using test structures to evaluate a fabrication of a wafer
US8990759B2 (en) 2003-08-25 2015-03-24 Tau-Metrix, Inc. Contactless technique for evaluating a fabrication of a wafer
US7220990B2 (en) 2003-08-25 2007-05-22 Tau-Metrix, Inc. Technique for evaluating a fabrication of a die and wafer
US7256055B2 (en) 2003-08-25 2007-08-14 Tau-Metrix, Inc. System and apparatus for using test structures inside of a chip during the fabrication of the chip
US7928750B2 (en) 2004-02-05 2011-04-19 Formfactor, Inc. Contactless interfacing of test signals with a device under test
EP1754074A4 (fr) * 2004-02-05 2011-10-19 Formfactor Inc Interfa age exempt de contact de signaux d'essai avec un dispositif a l'essai
EP1754074A2 (fr) * 2004-02-05 2007-02-21 FormFactor, Inc. Interfa age exempt de contact de signaux d'essai avec un dispositif a l'essai
WO2005101482A1 (fr) * 2004-04-05 2005-10-27 Stmicroelectronics Sa Procede de preparation de puces electroniques, et ensemble de puces en resultant
FR2868600A1 (fr) * 2004-04-05 2005-10-07 St Microelectronics Sa Procede de preparation de puces electroniques, et ensemble de puces en resultant
CN110031744A (zh) * 2017-12-12 2019-07-19 美光科技公司 用于测试半导体裸片的测试探针设备及相关系统及方法
CN110031744B (zh) * 2017-12-12 2022-04-26 美光科技公司 用于测试半导体裸片的测试探针设备及相关系统及方法
US11402426B2 (en) 2017-12-12 2022-08-02 Micron Technology, Inc. Inductive testing probe apparatus for testing semiconductor die and related systems and methods

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