FR2816108B1 - Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors - Google Patents

Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors

Info

Publication number
FR2816108B1
FR2816108B1 FR0013949A FR0013949A FR2816108B1 FR 2816108 B1 FR2816108 B1 FR 2816108B1 FR 0013949 A FR0013949 A FR 0013949A FR 0013949 A FR0013949 A FR 0013949A FR 2816108 B1 FR2816108 B1 FR 2816108B1
Authority
FR
France
Prior art keywords
pair
transistors
integrated circuit
oxide
corresponding integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0013949A
Other languages
English (en)
Other versions
FR2816108A1 (fr
Inventor
Laurence Boissonnet
Dominique Golanski
Bruno Rauber
Andre Granier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0013949A priority Critical patent/FR2816108B1/fr
Priority to US10/169,237 priority patent/US7015105B2/en
Priority to PCT/FR2001/003343 priority patent/WO2002037560A1/fr
Publication of FR2816108A1 publication Critical patent/FR2816108A1/fr
Application granted granted Critical
Publication of FR2816108B1 publication Critical patent/FR2816108B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
FR0013949A 2000-10-30 2000-10-30 Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors Expired - Fee Related FR2816108B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0013949A FR2816108B1 (fr) 2000-10-30 2000-10-30 Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors
US10/169,237 US7015105B2 (en) 2000-10-30 2001-10-26 Method of simultaneously making a pair of transistors with insulated gates having respectively a thin oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors
PCT/FR2001/003343 WO2002037560A1 (fr) 2000-10-30 2001-10-26 Procede de fabrication simultanee d"une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0013949A FR2816108B1 (fr) 2000-10-30 2000-10-30 Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors

Publications (2)

Publication Number Publication Date
FR2816108A1 FR2816108A1 (fr) 2002-05-03
FR2816108B1 true FR2816108B1 (fr) 2003-02-21

Family

ID=8855913

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0013949A Expired - Fee Related FR2816108B1 (fr) 2000-10-30 2000-10-30 Procede de fabrication simultanee d'une paire de transistors a grilles isolees ayant respectivement un oxyde fin et un oxyde epais, et circuit integre correspondant comprenant une telle paire de transistors

Country Status (3)

Country Link
US (1) US7015105B2 (fr)
FR (1) FR2816108B1 (fr)
WO (1) WO2002037560A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311858A (ja) * 2003-04-10 2004-11-04 Nec Electronics Corp 半導体集積回路装置
US20050247976A1 (en) * 2004-05-06 2005-11-10 Ting Steve M Notched spacer for CMOS transistors
JP4971593B2 (ja) * 2005-01-11 2012-07-11 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5592210B2 (ja) * 2010-09-09 2014-09-17 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9786755B2 (en) 2015-03-18 2017-10-10 Stmicroelectronics (Crolles 2) Sas Process for producing, from an SOI and in particular an FDSOI type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit
US9484417B1 (en) * 2015-07-22 2016-11-01 Globalfoundries Inc. Methods of forming doped transition regions of transistor structures
JP6917737B2 (ja) * 2017-03-13 2021-08-11 ユナイテッド・セミコンダクター・ジャパン株式会社 半導体装置の製造方法
CN110265359B (zh) * 2019-06-27 2020-07-24 长江存储科技有限责任公司 半导体器件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940004446B1 (ko) * 1990-11-05 1994-05-25 미쓰비시뎅끼 가부시끼가이샤 반도체장치의 제조방법
JPH06244366A (ja) * 1993-02-12 1994-09-02 Sony Corp Ｍｏｓトランジスタの製造方法
JPH07193200A (ja) * 1993-12-27 1995-07-28 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US5723352A (en) * 1995-08-03 1998-03-03 Taiwan Semiconductor Manufacturing Company Process to optimize performance and reliability of MOSFET devices
GB2337158B (en) * 1998-02-07 2003-04-02 United Semiconductor Corp Method of fabricating dual voltage mos transistors
US6157062A (en) * 1998-04-13 2000-12-05 Texas Instruments Incorporated Integrating dual supply voltage by removing the drain extender implant from the high voltage device

Also Published As

Publication number Publication date
WO2002037560A1 (fr) 2002-05-10
US20030155618A1 (en) 2003-08-21
US7015105B2 (en) 2006-03-21
FR2816108A1 (fr) 2002-05-03

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Effective date: 20070629