FR2681486B1 - Appareil de decodage de viterbi. - Google Patents
Appareil de decodage de viterbi.Info
- Publication number
- FR2681486B1 FR2681486B1 FR9210880A FR9210880A FR2681486B1 FR 2681486 B1 FR2681486 B1 FR 2681486B1 FR 9210880 A FR9210880 A FR 9210880A FR 9210880 A FR9210880 A FR 9210880A FR 2681486 B1 FR2681486 B1 FR 2681486B1
- Authority
- FR
- France
- Prior art keywords
- decoding apparatus
- viterbi decoding
- viterbi
- decoding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/395—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Artificial Intelligence (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26139791 | 1991-09-13 | ||
JP26139991 | 1991-09-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2681486A1 FR2681486A1 (fr) | 1993-03-19 |
FR2681486B1 true FR2681486B1 (fr) | 1997-04-25 |
Family
ID=26545053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9210880A Expired - Fee Related FR2681486B1 (fr) | 1991-09-13 | 1992-09-11 | Appareil de decodage de viterbi. |
Country Status (3)
Country | Link |
---|---|
US (1) | US5418795A (fr) |
DE (1) | DE4230521A1 (fr) |
FR (1) | FR2681486B1 (fr) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424881A (en) | 1993-02-01 | 1995-06-13 | Cirrus Logic, Inc. | Synchronous read channel |
JP3203941B2 (ja) * | 1994-03-24 | 2001-09-04 | 松下電器産業株式会社 | ビタビ復号装置 |
EP0677967A3 (fr) * | 1994-04-12 | 1997-07-23 | Gold Star Co | Décodeur Viterbi pour une télévision haute définition. |
US5841796A (en) * | 1995-03-14 | 1998-11-24 | Comsat Corporation | Apparatus and method for calculating viterbi path metric using exponentially-weighted moving average |
US5859861A (en) * | 1995-06-21 | 1999-01-12 | Hyundai Electronics Ind. Co., Ltd. | High speed viterbi decoder |
GB2309867A (en) * | 1996-01-30 | 1997-08-06 | Sony Corp | Reliability data in decoding apparatus |
KR100195741B1 (ko) * | 1996-07-01 | 1999-06-15 | 전주범 | 가변 레이트 비터비 복호화기 |
US5949820A (en) * | 1996-08-01 | 1999-09-07 | Nec Electronics Inc. | Method for optimizing an equalization and receive filter |
US5808573A (en) * | 1996-08-01 | 1998-09-15 | Nec Electronics Incorporated | Methods and structure for sampled-data timing recovery with reduced complexity and latency |
WO1998018209A1 (fr) * | 1996-10-24 | 1998-04-30 | Sony Corporation | Dispositif et appareil de decodage de viterbi |
US5781569A (en) * | 1996-10-28 | 1998-07-14 | Lsi Logic Corporation | Differential trellis decoding for convolutional codes |
US5914989A (en) * | 1997-02-19 | 1999-06-22 | Nec Electronics, Inc. | PRML system with reduced complexity maximum likelihood detector |
KR100442235B1 (ko) * | 1997-03-07 | 2004-10-22 | 엘지전자 주식회사 | 비터비 디코더의 가산-비교-선택(acs) 장치 |
US5974079A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Method and apparatus for encoding rate determination in a communication system |
US6148431A (en) * | 1998-03-26 | 2000-11-14 | Lucent Technologies Inc. | Add compare select circuit and method implementing a viterbi algorithm |
US6477680B2 (en) * | 1998-06-26 | 2002-11-05 | Agere Systems Inc. | Area-efficient convolutional decoder |
US6189126B1 (en) | 1998-11-05 | 2001-02-13 | Qualcomm Incorporated | Efficient trellis state metric normalization |
JP3700818B2 (ja) * | 1999-01-21 | 2005-09-28 | Necエンジニアリング株式会社 | 誤り訂正回路 |
KR100318912B1 (ko) * | 1999-04-28 | 2002-01-04 | 윤종용 | 이동통신시스템에서 구성복호기의 상태값 정규화 장치 및 방법 |
US6680980B1 (en) | 1999-09-03 | 2004-01-20 | Infineon Technologies North America Corp. | Supporting ME2PRML and M2EPRML with the same trellis structure |
US6415415B1 (en) | 1999-09-03 | 2002-07-02 | Infineon Technologies North America Corp. | Survival selection rule |
KR100365724B1 (ko) * | 2000-12-27 | 2002-12-31 | 한국전자통신연구원 | 이진 로그맵 알고리즘을 이용한 터보 복호기 및 그 구현방법 |
US20030053568A1 (en) * | 2001-09-08 | 2003-03-20 | Rad Farshid Rafiee | State metric rescaling for Viterbi decoding |
US6871316B1 (en) * | 2002-01-30 | 2005-03-22 | Lsi Logic Corporation | Delay reduction of hardware implementation of the maximum a posteriori (MAP) method |
US6928605B2 (en) * | 2002-03-29 | 2005-08-09 | Intel Corporation | Add-compare-select accelerator using pre-compare-select-add operation |
US7522678B2 (en) * | 2002-04-18 | 2009-04-21 | Infineon Technologies Ag | Method and apparatus for a data-dependent noise predictive viterbi |
TW536872B (en) * | 2002-07-03 | 2003-06-11 | Via Optical Solution Inc | Viterbi decoding device and method for multi-input data and multi-output data |
US7173985B1 (en) * | 2002-08-05 | 2007-02-06 | Altera Corporation | Method and apparatus for implementing a Viterbi decoder |
US7564930B1 (en) * | 2002-08-05 | 2009-07-21 | Altera Corporation | Method and apparatus for implementing a traceback processor for trellis decoding in a Viterbi decoder |
US7020831B2 (en) * | 2002-12-13 | 2006-03-28 | Broadcom Corporation | Pipelined add-compare-select circuits and methods, and applications thereof |
ITRM20030012A0 (it) * | 2003-01-14 | 2003-01-14 | St Microelectronics Srl | Metodo e sistema circuitale per la trasmissione sincrona di segnali digitali attraverso un bus. |
US7171609B2 (en) * | 2003-02-03 | 2007-01-30 | Verisilicon Holdings Company Ltd. | Processor and method for convolutional decoding |
US7213196B2 (en) * | 2003-02-04 | 2007-05-01 | International Business Machines Corporation | Method and system for indexing a decoder |
US7623585B2 (en) * | 2003-02-28 | 2009-11-24 | Maher Amer | Systems and modules for use with trellis-based decoding |
US7583762B2 (en) * | 2004-11-17 | 2009-09-01 | Agere Systems Inc. | Reduced-complexity multiple-input, multiple-output detection |
US7676001B2 (en) * | 2005-03-16 | 2010-03-09 | Agere Systems Inc. | MLD demapping using sub-metrics for soft-output MIMO detection and the like |
US7876847B2 (en) * | 2005-03-16 | 2011-01-25 | Agere Systems Inc. | Global minimum-based MLD demapping for soft-output MIMO detection |
US20070266303A1 (en) * | 2006-04-27 | 2007-11-15 | Qualcomm Incorporated | Viterbi decoding apparatus and techniques |
KR20080012434A (ko) * | 2006-08-03 | 2008-02-12 | 삼성전자주식회사 | 입력 메시지의 특성을 고려한 복호 장치 및 방법 |
JP2009110572A (ja) * | 2007-10-29 | 2009-05-21 | Funai Electric Co Ltd | 光ディスク記録再生装置 |
JP4585581B2 (ja) * | 2008-06-24 | 2010-11-24 | 株式会社東芝 | 最尤復号器および復号方法 |
US8554823B2 (en) * | 2010-09-02 | 2013-10-08 | Texas Instruments Incorporated | Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5919454A (ja) * | 1982-07-23 | 1984-01-31 | Nec Corp | メトリツク正規化回路 |
JPH07114378B2 (ja) * | 1986-01-31 | 1995-12-06 | 三菱電機株式会社 | ビタ−ビ復号器 |
JPS62233933A (ja) * | 1986-04-03 | 1987-10-14 | Toshiba Corp | ヴイタビ復号法 |
DE3721884A1 (de) * | 1987-07-02 | 1989-01-12 | Meyr Heinrich Prof Dr | Verfahren zur ausfuehrung des viterbi-algorithmus mit hilfe parallelverarbeitender strukturen |
US5295142A (en) * | 1989-07-18 | 1994-03-15 | Sony Corporation | Viterbi decoder |
US5208816A (en) * | 1989-08-18 | 1993-05-04 | At&T Bell Laboratories | Generalized viterbi decoding algorithms |
-
1992
- 1992-09-03 US US07/940,291 patent/US5418795A/en not_active Expired - Lifetime
- 1992-09-11 DE DE4230521A patent/DE4230521A1/de not_active Ceased
- 1992-09-11 FR FR9210880A patent/FR2681486B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2681486A1 (fr) | 1993-03-19 |
US5418795A (en) | 1995-05-23 |
DE4230521A1 (de) | 1993-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |