FR2645298B1 - Controleur d'acces direct en memoire - Google Patents

Controleur d'acces direct en memoire

Info

Publication number
FR2645298B1
FR2645298B1 FR8912124A FR8912124A FR2645298B1 FR 2645298 B1 FR2645298 B1 FR 2645298B1 FR 8912124 A FR8912124 A FR 8912124A FR 8912124 A FR8912124 A FR 8912124A FR 2645298 B1 FR2645298 B1 FR 2645298B1
Authority
FR
France
Prior art keywords
memory access
access controller
direct memory
direct
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8912124A
Other languages
English (en)
Other versions
FR2645298A1 (fr
Inventor
Naoichi Kitakami
Yuichi Nakao
Hiroyuki Kondo
Hideharu Toyomoto
Koji Tsuchihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2645298A1 publication Critical patent/FR2645298A1/fr
Application granted granted Critical
Publication of FR2645298B1 publication Critical patent/FR2645298B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
FR8912124A 1989-03-30 1989-09-15 Controleur d'acces direct en memoire Expired - Fee Related FR2645298B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1083186A JP2550496B2 (ja) 1989-03-30 1989-03-30 Ｄｍａコントローラ

Publications (2)

Publication Number Publication Date
FR2645298A1 FR2645298A1 (fr) 1990-10-05
FR2645298B1 true FR2645298B1 (fr) 1993-05-07

Family

ID=13795293

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8912124A Expired - Fee Related FR2645298B1 (fr) 1989-03-30 1989-09-15 Controleur d'acces direct en memoire

Country Status (5)

Country Link
US (1) US5031097A (fr)
JP (1) JP2550496B2 (fr)
KR (1) KR920008460B1 (fr)
DE (1) DE3936339C2 (fr)
FR (1) FR2645298B1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04363745A (ja) * 1991-05-17 1992-12-16 Toshiba Corp Ｄｍａコントローラ
JPH0567039A (ja) * 1991-09-06 1993-03-19 Toshiba Corp Ｄｍａチヤネル制御装置
US5721954A (en) * 1992-04-13 1998-02-24 At&T Global Information Solutions Company Intelligent SCSI-2/DMA processor
US5598579A (en) * 1994-04-25 1997-01-28 Compaq Computer Corporation System fpr transferring data between two buses using control registers writable by host processor connected to system bus and local processor coupled to local bus
US5864712A (en) * 1995-03-17 1999-01-26 Lsi Logic Corporation Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable environment
DE69614291T2 (de) * 1995-03-17 2001-12-06 Lsi Logic Corp., Fort Collins (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5826106A (en) * 1995-05-26 1998-10-20 National Semiconductor Corporation High performance multifunction direct memory access (DMA) controller
JP2002041445A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
KR20020021739A (ko) * 2000-09-16 2002-03-22 박종섭 디엠에이 제어기
US7380069B2 (en) * 2004-11-19 2008-05-27 Marvell International Technology Ltd. Method and apparatus for DMA-generated memory write-back
US7383363B2 (en) * 2004-11-20 2008-06-03 Marvell International Technology Ltd. Method and apparatus for interval DMA transfer access
KR100703406B1 (ko) * 2005-02-04 2007-04-03 삼성전자주식회사 Ｄｍａ 제어 장치 및 방법
JP2007219641A (ja) * 2006-02-14 2007-08-30 Oki Electric Ind Co Ltd ダイレクトメモリアクセスコントローラ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1132265A (fr) * 1978-12-26 1982-09-21 Minoru Inoshita Appareil a priorites alternees a memoire a acces direct
IT1209338B (it) * 1980-07-24 1989-07-16 Sits Soc It Telecom Siemens Disposizione circuitale per il trasferimento di dati tra la memoria di un elaboratore elettronico e le unita' di interfaccia delle periferiche ad esso collegate.
US4750107A (en) * 1985-01-07 1988-06-07 Unisys Corporation Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system

Also Published As

Publication number Publication date
US5031097A (en) 1991-07-09
KR920008460B1 (ko) 1992-09-30
KR900015009A (ko) 1990-10-25
JPH02259861A (ja) 1990-10-22
DE3936339A1 (de) 1990-10-04
DE3936339C2 (de) 2000-08-31
JP2550496B2 (ja) 1996-11-06
FR2645298A1 (fr) 1990-10-05

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Legal Events

Date Code Title Description
D6 Patent endorsed licences of rights
ST Notification of lapse

Effective date: 20080531