FR2641126B1 - - Google Patents

Info

Publication number
FR2641126B1
FR2641126B1 FR898906415A FR8906415A FR2641126B1 FR 2641126 B1 FR2641126 B1 FR 2641126B1 FR 898906415 A FR898906415 A FR 898906415A FR 8906415 A FR8906415 A FR 8906415A FR 2641126 B1 FR2641126 B1 FR 2641126B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR898906415A
Other languages
French (fr)
Other versions
FR2641126A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2641126A1 publication Critical patent/FR2641126A1/fr
Application granted granted Critical
Publication of FR2641126B1 publication Critical patent/FR2641126B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • H01L21/32053Deposition of metallic or metal-silicide layers of metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53271Conductive materials containing semiconductor material, e.g. polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/019Contacts of silicides
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/026Deposition thru hole in mask
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/147Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR8906415A 1988-12-24 1989-05-17 Method of forming low-resistance contacts with pre-ohmic regions of n<+> and p<+> types in integrated circuits Granted FR2641126A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880017435A KR930004295B1 (ko) 1988-12-24 1988-12-24 Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법

Publications (2)

Publication Number Publication Date
FR2641126A1 FR2641126A1 (en) 1990-06-29
FR2641126B1 true FR2641126B1 (US20030220297A1-20031127-C00009.png) 1992-11-27

Family

ID=19280663

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8906415A Granted FR2641126A1 (en) 1988-12-24 1989-05-17 Method of forming low-resistance contacts with pre-ohmic regions of n<+> and p<+> types in integrated circuits

Country Status (6)

Country Link
US (1) US5070038A (US20030220297A1-20031127-C00009.png)
JP (1) JP2528961B2 (US20030220297A1-20031127-C00009.png)
KR (1) KR930004295B1 (US20030220297A1-20031127-C00009.png)
DE (1) DE3908676A1 (US20030220297A1-20031127-C00009.png)
FR (1) FR2641126A1 (US20030220297A1-20031127-C00009.png)
GB (1) GB2226446B (US20030220297A1-20031127-C00009.png)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629218A (en) * 1989-12-19 1997-05-13 Texas Instruments Incorporated Method for forming a field-effect transistor including a mask body and source/drain contacts
KR940008936B1 (ko) * 1990-02-15 1994-09-28 가부시끼가이샤 도시바 고순도 금속재와 그 성질을 이용한 반도체 장치 및 그 제조방법
US5288664A (en) * 1990-07-11 1994-02-22 Fujitsu Ltd. Method of forming wiring of semiconductor device
KR920010759A (ko) * 1990-11-16 1992-06-27 원본미기재 저 저항 접점을 제조하는 방법
EP0496169A1 (en) * 1991-01-25 1992-07-29 AT&T Corp. Method of integrated circuit fabrication including filling windows with conducting material
KR100228619B1 (ko) * 1991-03-05 1999-11-01 아치 케이. 말론 자기-정합 접점 형성 방법 및 구조
US5278096A (en) * 1991-12-23 1994-01-11 At&T Bell Laboratories Transistor fabrication method
US5416034A (en) 1993-06-30 1995-05-16 Sgs-Thomson Microelectronics, Inc. Method of making resistor with silicon-rich silicide contacts for an integrated circuit
JP2699839B2 (ja) * 1993-12-03 1998-01-19 日本電気株式会社 半導体装置の製造方法
US6200871B1 (en) * 1994-08-30 2001-03-13 Texas Instruments Incorporated High performance self-aligned silicide process for sub-half-micron semiconductor technologies
TW316326B (en) * 1996-09-21 1997-09-21 United Microelectronics Corp Manufacturing method of word line
DE19648733C2 (de) * 1996-09-21 2002-11-07 United Microelectronics Corp Verfahren zur Herstellung von Wortzeilen in dynamischen Schreib-Lesespeichern
JP3413078B2 (ja) * 1997-10-06 2003-06-03 キヤノン株式会社 光電変換装置と密着型イメージセンサ
US6048791A (en) * 1998-03-31 2000-04-11 Kabushiki Kaisha Toshiba Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method
JP2001068670A (ja) * 1999-08-30 2001-03-16 Nec Corp 半導体装置の製造方法
JP4209178B2 (ja) * 2002-11-26 2009-01-14 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7407882B1 (en) 2004-08-27 2008-08-05 Spansion Llc Semiconductor component having a contact structure and method of manufacture
US8018015B2 (en) * 2005-06-29 2011-09-13 Micron Technology, Inc. Buried conductor for imagers

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4364166A (en) * 1979-03-01 1982-12-21 International Business Machines Corporation Semiconductor integrated circuit interconnections
JPS57186341A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor device
US4359490A (en) * 1981-07-13 1982-11-16 Fairchild Camera & Instrument Corp. Method for LPCVD co-deposition of metal and silicon to form metal silicide
JPS59150421A (ja) * 1983-02-10 1984-08-28 Toshiba Corp 半導体装置の製造方法
GB2139420B (en) * 1983-05-05 1987-04-29 Standard Telephones Cables Ltd Semiconductor devices
US4545116A (en) * 1983-05-06 1985-10-08 Texas Instruments Incorporated Method of forming a titanium disilicide
JPS60143648A (ja) * 1983-08-23 1985-07-29 Nec Corp 半導体装置の製造方法
JPS60119750A (ja) * 1983-12-02 1985-06-27 Hitachi Ltd 半導体装置の製造方法
JPS60193380A (ja) * 1984-03-15 1985-10-01 Nec Corp 半導体装置の製造方法
US4619035A (en) * 1984-06-23 1986-10-28 Nippon Gakki Seizo Kabushiki Kaisha Method of manufacturing a semiconductor device including Schottky barrier diodes
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
JPS6158866A (ja) * 1984-08-30 1986-03-26 三菱マテリアル株式会社 高融点金属珪化物基複合材料の製造法
JPS61294816A (ja) * 1985-06-21 1986-12-25 Matsushita Electronics Corp 半導体装置の製造方法
ATE46791T1 (de) * 1985-07-29 1989-10-15 Siemens Ag Verfahren zum selektiven auffuellen von in isolationsschichten geaetzten kontaktloechern mit metallisch leitenden materialien bei der herstellung von hoechstintegrierten halbleiterschaltungen sowie eine vorrichtung zur durchfuehrung des verfahrens.
US4751198A (en) * 1985-09-11 1988-06-14 Texas Instruments Incorporated Process for making contacts and interconnections using direct-reacted silicide
US4818723A (en) * 1985-11-27 1989-04-04 Advanced Micro Devices, Inc. Silicide contact plug formation technique
JPS62213277A (ja) * 1986-03-14 1987-09-19 Nec Corp 半導体装置の製造方法
JPH0779136B2 (ja) * 1986-06-06 1995-08-23 株式会社日立製作所 半導体装置
JPS63116A (ja) * 1986-06-19 1988-01-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6377117A (ja) * 1986-09-19 1988-04-07 Fujitsu Ltd 半導体装置の製造方法
JPS63120419A (ja) * 1986-11-10 1988-05-24 Matsushita Electronics Corp 半導体装置の製造方法
NL8700820A (nl) * 1987-04-08 1988-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JPH06276518A (ja) * 1993-03-22 1994-09-30 Sony Corp 画像処理装置
JPH06321829A (ja) * 1993-05-07 1994-11-22 Taiho Yakuhin Kogyo Kk α,α−ジメチルシクロヘキサンカルビノール誘導体又はその塩

Also Published As

Publication number Publication date
KR930004295B1 (ko) 1993-05-22
JPH02194524A (ja) 1990-08-01
GB2226446A (en) 1990-06-27
GB2226446B (en) 1993-02-24
GB8921421D0 (en) 1989-11-08
FR2641126A1 (en) 1990-06-29
DE3908676A1 (de) 1990-06-28
US5070038A (en) 1991-12-03
JP2528961B2 (ja) 1996-08-28
KR900010993A (ko) 1990-07-11

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