FR2573248A1 - METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR AND TRANSISTOR THUS MANUFACTURED - Google Patents

Abstract

A.PROCESS OF MANUFACTURING A THIN FILM TRANSISTOR. B. PROCESS CHARACTERIZED IN THAT WE MAKE A SEMICONDUCTOR POLYCRYSTALLINE 2 FILM ON A PREDETERMINED SUBSTRATE 1, PREDETERMINATED IONS ARE IMPLANTED IN THE THIN POLYCRYSTALLINE SEMICONDUCTOR FILM TO FORM A SEMI-CONDUCTIVE FILM INTO THE THIN POLYCRYSTALLINE FILM, ON REALIZED THIN 3 GATE INSULATION 8 AND A GATE ELECTRODE 7 ON THE AMORPHIC SEMICONDUCTOR FILM 4, IMPURITIES FORMING SOURCE REGION 9 AND DRAIN REGION 10 ARE DOPED IN THE AMORPHIC SEMICONDUCTOR FILM 4 USING THE AMORPHIC SEMICONDUCTOR FILM 4. ELECTRODE OF DOOR 7 AND THE INSULATING FILM OF DOOR 8 LIKE MASKS, AND AN ANNULMENT IS PERFORMED TO DEVELOP IN SOLID PHASE THE THIN AMORPHIC SEMICONDUCTOR FILM AND AT THE SAME TIME TO ELECTRICALLY ACTIVATE THE IMPURITIES AND FORM THE SOURCE REGION AND THE REGION DE DRAIN 9, 10. C. THE INVENTION RELATES TO THE MANUFACTURE OF THIN FILM TRANSISTORS.

Description

Method of manufacturing a thin film transistor

and transistor thus manufactured.

  The present invention relates to a method of manufacturing a thin film transistor and

the transistor thus manufactured.

  BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a method of manufacturing a thin film transistor

  (still called "TFT transistor") and more particularly

  a method for manufacturing a TFT transistor

polysilicon.

Description of the prior art:

  We usually make a transistor

  polysilicon TFT torch in a low temperature process

described below.

  As represented in FIG. 1A, a polysilicon film 2 is deposited according to a low-pressure chemical vapor deposition method (also called "LPCVD process") on a glass support 1 at a temperature equal to or less than 600.degree. The glass support has a melting point which is generally

  around 680 C. The ions of an electrical element-

  Inactive materials such as Si + are implanted in the polysilicon film 2 to form an amorphous silicon film 3 as shown in FIG. 1B. The structure obtained is annealed at a temperature of between 500 ° C. and 600 ° C. in order to induce a solid phase development of the

  amorphous silicon film 3 so that the silicone film

  amorphous cium 3 crystallizes. This results in a polysilicon film 4 having larger crystal grain sizes (not shown) than those of the polysilicon film 2 as realized (see FIG. 1C). According to

  Figure 1D, a chemical attack on a predefined

  finished polysilicon film 4 according to a pre-

  determined. A SiO2 silica film is deposited by means of a

  yielding chemical vapor deposition (CVD process) to cover the entire surface of the resulting structure, working at a temperature of about 400 C. Then, a film such as a 6 Mo film is projected on the film 5 silica SiO2. The predetermined portions of films 6 and 5 of Mo and SiO 2 are sequentially etched

  forming a gate electrode 7, Mo having a pre-existing schematic

  determined and a gate insulating film 8 formed of a SiO2 silica diagram which is the same as that of the electrode

  of door 7, Mo. Then, one carries out an ion implantation

  n-type impurity, for example, phosphorus (P) in the polysilicon film 4 at a higher concentration by using as masks the gate electrode 7 and the gate insulating film 8 (the phosphor ions of the phosphoric acid film). polysilicon 4 are represented by small circles in Figure 1E). The resulting structure is annealed

  at a temperature of about 600 C to activate electric-

  impurities and thus form a source region 9 and an n-type drain region 10 as shown in FIG.

Figure 1F.

  According to FIG. 1G, a SiO2 silica film 11 is deposited by a CVD process to form a passivation film at a temperature of approximately 400 ° C.

  to cover the entire surface. Then, we remove by attack

  as chemical predetermined portions of the SiO2 silica film 11 to form the contact holes 11a and 11b. Aluminum is deposited to cover the entire surface and chemically etched to form the electrodes 12 and 13 in the contact holes 11a and 11b thereby preparing a polysilicon TFT transistor to

channel n.

  The conventional method of manufacturing the polysilicon TFT transistor while working at low temperature has the following drawback: the annealing for the solid phase development of the amorphous silicon film 3 must be distinct from the electrical activation annealing of the impurities forming the source 9 and the drain region 10, which complicates the manufacturing process. In addition, the part of the ionically implanted impurities in the polysilicon film 4 is present at the grain boundaries in the film.

  of polysicilium 4, it is difficult to activate electrical-

  impurities at the grain boundaries by annealing. That's why, total return

  impurity activation is weak. The ions of im-

  doping purities are necessarily submitted in a

  certain extent to a canal effect during implanta-

  ionic contamination of the impurities in the polysilicon film 4.

  That is why after the annealing, the impurities of the source region 9 and the drain region 10 are not

activated uniformly.

  A TFT transistor according to the prior art

  This reference is given as an example in the papers of the 45th Conference of Japan Society of Applied Physics (1984) No. 14pA-4 to 14p-A-6, PP. 407-408. This reference describes a refinement

  to a polysilicon TFT transistor whose characteristics

  of the transistor are perfected thanks to a film of

  ultra-thin polysilicon; These improvements concern

  the growth effect of the solid phase crystal grains and the conduction characteristics of the ultra-thin polysilicon film obtained by oxidation

  thermal; another refinement of the characteristics

  of the transistor results from the annealing of the structure in a hydrogen atmosphere at a temperature of 400 ° C. after forming a Si 3 N 4 film by a process

  Plasma CVD on the ultra-polysilicon TFT transistor

thin to get this structure.

PURPOSE AND SUMMARY OF THE INVENTION:

  It is an object of the present invention to provide a method of manufacturing a thin film transistor that overcomes the above disadvantages of a

conventional thin film transistor.

  For this purpose, the invention relates to a method for manufacturing a thin-film transistor characterized in that a thin polycrystalline semiconductor film is produced on a predetermined support,

  implements predetermined ions into the semiconductor film

  thin polycrystalline fiber to form a semi-conductive

  thin amorphous film, an insulation film of

  gate and a gate electrode on the semiconductor film.

  In the amorphous thin film, a source region and a drain region are formed by doping impurities in the thin amorphous semiconductor film using the gate electrode and the door insulating film as masks.

  for solid phase development the semiconductor film

  amorphous and at the same time to activate

  impurities and form the source region and

the drain region.

  According to the method described above, the annealing for the solid phase development of the thin amorphous semiconductor film does not have to be distinct from the electrical activation annealing of the impurities to form the source region and the drain region. The manufacturing process can thus be simplified. In addition, the impurities of the source and drain regions can be uniformly activated compared to the

conventional transistors.

SHORT DESCRIPTION OF THE DRAWINGS:

  The present invention will be described in more detail with the aid of the accompanying drawings, in which: FIGS. 1A-1G are views in

  schematic section used to explain the manufacturing steps

  cation of a conventional polysilicon TFT transistor,

  in a known low temperature process.

  FIGS. 2A-2C are sectional views for explaining the steps of manufacturing an n-channel polysilicon TFT transistor according to FIG.

method of the invention.

  DETAILED DESCRIPTION OF A PREFERENTIAL EMBODIMENT:

  A method of manufacturing a tran-

  polysilicon TFT sistor will be given below as

  example of an embodiment of the manufacturing process

  according to the invention with reference to the drawings. In

  FIGS. 2A-2C will use the same numerical references

  than the figures lA-lG to designate the same ele-

  ments and the detailed description of which will not be repeated

where appropriate.

  A film of polysilicon o (2) with a thickness of approximately 800 A according to the LPCVD method is deposited on a glass support 1 at a temperature of between approximately 580 ° C. and 600 ° C., proceeding as in

Figure lA.

  Si + ions are implanted in the polysilicon film (2) with an acceleration energy of 40 keV and a dosage of between 1015 cm-2 to 1015 cm -2 to form an amorphous silicon film 3

  as has been described using Figure 1B.

  According to FIG. 2A, a predetermined portion of the amorphous silicon film 3 is etched to obtain a predetermined pattern. A silica SiO 2 film having a thickness of about 1000 A is deposited using the LPCVD process; this deposit is made over the entire exposed surface, in the same manner as has been described with reference to FIG. 1D. A 6 O film of Mo with a thickness of the order of 3000 A is projected onto the surface

SiO2 silica film.

  According to Fig. 2B, sequential portions of the Mo film 6 and the SiO 2 silica film 5 are sequentially etched to form a gate electrode 7 and a gate insulating film 8 as described in Fig. 1E. Then, P + ions are implanted in the amorphous silicon film 3 by using as masks the gate electrode 7 and the insulating film of

  gate 8 (the phosphorus ions of the amorphous silicon

  phe 3 are represented by small circles in Figure 2B). * The annealing is done at a temperature of about 600 C to develop in solid phase the

  amorphous silicon film 3 and form a polysilicon film

  4 as shown in FIG. 2C. At the same time, the doped phosphorus ions are electrically activated to form the source region 9 and the n-type drain region 10. Then, a film 11 of silica SIO2 is produced as a passivation film and electrodes 12 and 13 are produced to prepare a polysilicon TFT transistor.

  n-channel in the same way as in Figure 1G.

  According to the embodiment described

  above, the solid phase growth of the silicone film

  and the activation of the impurities to form the source region 9 and the drain region 10 can be accomplished in a single annealing operation. It is

  why compared to the conventional process

  1A-G1C, a step of annealing can be omitted, which simplifies the manufacturing process. the

  during the annealing process described above, the development of

  solid phase of the amorphous silicon film 3 is

  simultaneously with activation of implanted impurities.

  This is why the impurities of the source region 9 and

  of the drain region 10 can be activated uniformly

  compared to a conventional transistor.

  In the annealing process described above

  above, the nuclei of crystals tend to form in

  regions of ion implantation of phosphorus in the

  inside the amorphous silicon film 3 when growing

  this in solid phase of film 3. The development of nuclei

  to form small crystals, then grains of crystals

  rate of large size thus increases the crystal grain size of the source region 9 and the

  drain region 10 compared to the corresponding regions

  of the classical transistor. This is why as the surface of the grain boundary is decreased compared to that of a conventional transistor, it is possible to

  effectively activate impurities in a way that

  corresponds to the decrease of the surface of the borders of the grains. By using small crystals as seed crystals, the development of the crystals proceeds in a direction parallel to the surface of the amorphous silicon film 3. The crystal grain size of the polysilicon film 4 obtained by the solid phase development described above in FIG. the channel region 4a

  (FIG. 2C) is greater than that of a conventional transistor

  if that. A channel is made in the channel region during the implementation of the TFT transistor. This is why in this embodiment, the mobility of the carriers of the TFT transistor is greater than that of a transistor

Classic TFT.

  In the above embodiment, as the impurities are implanted as ions to constitute the source region 9 and the drain region 10 after implantation of the polysilicon film 2 with Si + ions to form the amorphous silicon film 3, there is virtually no channel effect for the impurities thus implanted. The profile of the impurities implanted in the TFT transistor according to this embodiment is more uniform than that of the conventional TFT transistor. Therefore, the impurities of the source region 9 and the drain region 10 can be activated more

  uniform than in the conventional TFT transistor.

  The present invention is given by way of example in the particular embodiment

  described above without this embodiment constituting

  is a limitation. Different variants and modifications

  tions may be made within the scope and spirit of the invention. For example, ions of an electrically inactive element such as F + may be used instead

  of Si + as a source-of ion implantation for transfor-

  sea the polysilicon film 2 into an amorphous film. The ion implantation source forming the source region 9 and the drain region 10 is not limited either to P + but may correspond to the ions of other elements as appropriate. In addition, the material of the gate electrode 7 may be another refractory metal such as for example

  W including Mo or a silicide of a metal refra-

  silent. The polysilicon film 2 can be replaced by another thin polycrystalline semiconductor film. The

  polysilicon film 2 can be obtained by another

  than the arc discharge decomposition process (CVD plasma process) in place of the LPCVD process. Thus, the method of decomposition by arc discharge makes it possible to produce a film of polysilicon 2 at a

  temperature equal to or less than 2000C.

RE VE N D I CA TI 0 N S

  ) Method of manufacturing a tran-

  thin film sistor characterized in that a polycrystalline semiconductor film (2) is made on a predetermined support (1), predetermined ions are implanted in the thin polycrystalline semiconductor film to form a thin amorphous semiconductor film (3). ), a gate insulating film (8) and a gate electrode (7) are made on the amorphous semiconductor film (4), impurities forming the source region (9) and the drain region are doped. (10) in the amorphous semiconductor film (4) using the gate electrode (7) and the gate insulating film (8) as masks, and annealing is performed.

  developing in solid phase the amorphous semiconductor film

  thin phe and at the same time to electrically activate the impurities and form the source region and region

drain (9, 10).

  Method according to claim 1,

  characterized in that the semiconductor polycrystalline film

  tallin (2) is a polysilicon film.

  Process according to Claim 2, characterized in that the ions are Si + ions according to

-2 15 -2

  a dosage of 1015 cm 2 to 5 x 1015 cm 2 4) Method according to any one

  Claims 2 or 3, characterized in that the film

  polysilicon (2) is produced by the chemical vapor deposition method, at low pressure on a support, at

  a temperature of between 580 C and 600 C.

 ) Method according to any one

  Claims 1 to 4, characterized in that the

  predetermined port (1) is a glass support.

  6) TFT thin film transistor, characterized in that it is obtained by the implementation

  process according to any one of claims 1 to 5.