FR2570205A1 - Procede d'interruption par un seul rythmeur pour realiser des transmissions sur plusieurs acces - Google Patents

Procede d'interruption par un seul rythmeur pour realiser des transmissions sur plusieurs acces Download PDF

Info

Publication number
FR2570205A1
FR2570205A1 FR8513249A FR8513249A FR2570205A1 FR 2570205 A1 FR2570205 A1 FR 2570205A1 FR 8513249 A FR8513249 A FR 8513249A FR 8513249 A FR8513249 A FR 8513249A FR 2570205 A1 FR2570205 A1 FR 2570205A1
Authority
FR
France
Prior art keywords
sub
bit
access
bits
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR8513249A
Other languages
English (en)
French (fr)
Inventor
Steve Dumbovic
Mark A Dempsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Illinois Tool Works Inc
Original Assignee
Illinois Tool Works Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Illinois Tool Works Inc filed Critical Illinois Tool Works Inc
Publication of FR2570205A1 publication Critical patent/FR2570205A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
  • Computer And Data Communications (AREA)
  • Bidirectional Digital Transmission (AREA)
FR8513249A 1984-09-07 1985-09-06 Procede d'interruption par un seul rythmeur pour realiser des transmissions sur plusieurs acces Pending FR2570205A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/648,869 US4707782A (en) 1984-09-07 1984-09-07 Method for effecting one timer interrupt for multiple port communication

Publications (1)

Publication Number Publication Date
FR2570205A1 true FR2570205A1 (fr) 1986-03-14

Family

ID=24602556

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8513249A Pending FR2570205A1 (fr) 1984-09-07 1985-09-06 Procede d'interruption par un seul rythmeur pour realiser des transmissions sur plusieurs acces

Country Status (5)

Country Link
US (1) US4707782A (enExample)
JP (1) JPS6167165A (enExample)
DE (1) DE3531887A1 (enExample)
FR (1) FR2570205A1 (enExample)
GB (1) GB2164178B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2183851C2 (ru) * 2000-09-28 2002-06-20 Открытое акционерное общество "Центральное конструкторское бюро связи" Устройство для сопряжения периферийных устройств с эвм-персональным компьютером
RU2194301C2 (ru) * 2001-01-09 2002-12-10 Военный университет связи Устройство подключения источников информации к общей магистрали
RU2275682C2 (ru) * 2003-04-22 2006-04-27 Общество с ограниченной ответственностью "Юник Ай Сиз" Устройство для передачи данных между компьютером и периферийными устройствами
US20140007115A1 (en) * 2012-06-29 2014-01-02 Ning Lu Multi-modal behavior awareness for human natural command control

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4241398A (en) * 1978-09-29 1980-12-23 United Technologies Corporation Computer network, line protocol system
US4449202A (en) * 1981-12-04 1984-05-15 Ncr Corporation Full duplex integrated circuit communication controller
EP0094800B1 (en) * 1982-05-14 1989-01-11 Production Control Information (Pci) Limited Production control system, especially for garment manufacture
US4476558A (en) * 1982-07-29 1984-10-09 Northern Telecom Limited Time compression multiplex digital transmission system
US4547880A (en) * 1983-05-13 1985-10-15 Able Computer Communication control apparatus for digital devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, vol. 32, no. 16, 9 août 1984, pages 209-214,216,218,222, Waseca, MN, Denville, NJ, US; A. GOLDBERGER et al.: "Dual-UART chip assumes broader processing role in asynchronous systems" *
ELEKTRONIK, vol. 31, no. 23, 19 novembre 1982, pages 91-94, Munich, DE; P. VON BECHEN: "Asynchrone Kommunikation mit VLSI-Schaltung preiswert realisiert" *

Also Published As

Publication number Publication date
JPH0470658B2 (enExample) 1992-11-11
JPS6167165A (ja) 1986-04-07
US4707782A (en) 1987-11-17
GB2164178A (en) 1986-03-12
DE3531887A1 (de) 1986-03-20
GB8521499D0 (en) 1985-10-02
GB2164178B (en) 1988-05-18

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