FR2543738B1 - Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation - Google Patents

Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation

Info

Publication number
FR2543738B1
FR2543738B1 FR8405074A FR8405074A FR2543738B1 FR 2543738 B1 FR2543738 B1 FR 2543738B1 FR 8405074 A FR8405074 A FR 8405074A FR 8405074 A FR8405074 A FR 8405074A FR 2543738 B1 FR2543738 B1 FR 2543738B1
Authority
FR
France
Prior art keywords
alignment
self
integrated circuit
polycrystalline silicon
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8405074A
Other languages
English (en)
French (fr)
Other versions
FR2543738A1 (fr
Inventor
Pierangelo Pansana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
ATES Componenti Elettronici SpA
SGS ATES Componenti Elettronici SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATES Componenti Elettronici SpA, SGS ATES Componenti Elettronici SpA filed Critical ATES Componenti Elettronici SpA
Publication of FR2543738A1 publication Critical patent/FR2543738A1/fr
Application granted granted Critical
Publication of FR2543738B1 publication Critical patent/FR2543738B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
FR8405074A 1983-03-31 1984-03-30 Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation Expired FR2543738B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20391/83A IT1218344B (it) 1983-03-31 1983-03-31 Processo per l'autoallineamento di un doppio strato di silicio policristallino,in un dispositivo a circuito integrato,mediante un' operazione di ossidazione

Publications (2)

Publication Number Publication Date
FR2543738A1 FR2543738A1 (fr) 1984-10-05
FR2543738B1 true FR2543738B1 (fr) 1986-06-20

Family

ID=11166285

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8405074A Expired FR2543738B1 (fr) 1983-03-31 1984-03-30 Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation

Country Status (7)

Country Link
US (1) US4488931A (https=)
JP (1) JPS59211282A (https=)
DE (1) DE3411960A1 (https=)
FR (1) FR2543738B1 (https=)
GB (1) GB2138632B (https=)
IT (1) IT1218344B (https=)
NL (1) NL8400960A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213192B (it) * 1984-07-19 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'.
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
US4683640A (en) * 1986-04-15 1987-08-04 Rca Corporation Method of making a floating gate memory cell
US4735919A (en) * 1986-04-15 1988-04-05 General Electric Company Method of making a floating gate memory cell
US4808555A (en) * 1986-07-10 1989-02-28 Motorola, Inc. Multiple step formation of conductive material layers
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5272100A (en) * 1988-09-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode and manufacturing method therefor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1540450A (en) * 1975-10-29 1979-02-14 Intel Corp Self-aligning double polycrystalline silicon etching process
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
EP0002107A3 (en) * 1977-11-17 1979-09-05 Rca Corporation Method of making a planar semiconductor device
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4355455A (en) * 1979-07-19 1982-10-26 National Semiconductor Corporation Method of manufacture for self-aligned floating gate memory cell
FR2468185A1 (fr) * 1980-10-17 1981-04-30 Intel Corp Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite

Also Published As

Publication number Publication date
DE3411960C2 (https=) 1992-04-02
GB8408434D0 (en) 1984-05-10
IT8320391A0 (it) 1983-03-31
JPS59211282A (ja) 1984-11-30
FR2543738A1 (fr) 1984-10-05
GB2138632B (en) 1986-10-15
DE3411960A1 (de) 1984-10-04
IT1218344B (it) 1990-04-12
US4488931A (en) 1984-12-18
GB2138632A (en) 1984-10-24
NL8400960A (nl) 1984-10-16

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Legal Events

Date Code Title Description
D6 Patent endorsed licences of rights
ST Notification of lapse