FR2535128B1 - Circuit d'interface pour generateurs de signaux de synchronisme a deux phases non superposees - Google Patents

Circuit d'interface pour generateurs de signaux de synchronisme a deux phases non superposees

Info

Publication number
FR2535128B1
FR2535128B1 FR8316774A FR8316774A FR2535128B1 FR 2535128 B1 FR2535128 B1 FR 2535128B1 FR 8316774 A FR8316774 A FR 8316774A FR 8316774 A FR8316774 A FR 8316774A FR 2535128 B1 FR2535128 B1 FR 2535128B1
Authority
FR
France
Prior art keywords
superimposed
interface circuit
signal generators
phase non
synchronism signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8316774A
Other languages
English (en)
Other versions
FR2535128A1 (fr
Inventor
Guido Torelli
Daniele Devecchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
ATES Componenti Elettronici SpA
SGS ATES Componenti Elettronici SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATES Componenti Elettronici SpA, SGS ATES Componenti Elettronici SpA filed Critical ATES Componenti Elettronici SpA
Publication of FR2535128A1 publication Critical patent/FR2535128A1/fr
Application granted granted Critical
Publication of FR2535128B1 publication Critical patent/FR2535128B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
FR8316774A 1982-10-22 1983-10-21 Circuit d'interface pour generateurs de signaux de synchronisme a deux phases non superposees Expired FR2535128B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8223869A IT1210945B (it) 1982-10-22 1982-10-22 Circuito di interfaccia per generatori di segnali di sincronismo a due fasi nonsovrapposte.

Publications (2)

Publication Number Publication Date
FR2535128A1 FR2535128A1 (fr) 1984-04-27
FR2535128B1 true FR2535128B1 (fr) 1986-04-25

Family

ID=11210534

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8316774A Expired FR2535128B1 (fr) 1982-10-22 1983-10-21 Circuit d'interface pour generateurs de signaux de synchronisme a deux phases non superposees

Country Status (5)

Country Link
US (1) US4587441A (fr)
DE (1) DE3338206A1 (fr)
FR (1) FR2535128B1 (fr)
GB (1) GB2128832B (fr)
IT (1) IT1210945B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110811A (ja) * 1986-10-28 1988-05-16 Mitsubishi Electric Corp クロツクジエネレ−タ
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
US4816700A (en) * 1987-12-16 1989-03-28 Intel Corporation Two-phase non-overlapping clock generator
US5059837A (en) * 1989-02-13 1991-10-22 Ibm Data dependent variable time delay circuit
US5182468A (en) * 1989-02-13 1993-01-26 Ibm Corporation Current limiting clamp circuit
EP0418419B1 (fr) * 1989-09-22 1994-12-14 Deutsche ITT Industries GmbH Générateur à deux phases
US5389831A (en) * 1992-12-17 1995-02-14 Vlsi Technology, Inc. Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew
KR970005574B1 (ko) * 1994-08-24 1997-04-17 현대전자산업 주식회사 노이즈 감쇠 출력 버퍼
JP3330746B2 (ja) * 1994-09-09 2002-09-30 新日本製鐵株式会社 ブートストラップ回路
DE69613118T2 (de) * 1996-07-31 2001-10-25 St Microelectronics Srl Verfahren und Schaltung zur Ladungssteuerung eines Bootstrap-Kondensators in einem schaltenden spannungsreduzierenden Regler
JP5886128B2 (ja) * 2011-05-13 2016-03-16 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5022593B1 (fr) * 1970-06-15 1975-07-31
US3986046A (en) * 1972-07-24 1976-10-12 General Instrument Corporation Dual two-phase clock system
US3927334A (en) * 1974-04-11 1975-12-16 Electronic Arrays MOSFET bistrap buffer
US3961269A (en) * 1975-05-22 1976-06-01 Teletype Corporation Multiple phase clock generator
JPS53106552A (en) * 1977-02-28 1978-09-16 Toshiba Corp Waveform shaping circuit
DE2837882C2 (de) * 1978-08-30 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Taktformer für integrierte Halbleiter-Digitalschaltungen
DE2837855C2 (de) * 1978-08-30 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Impulswandler zur Taktversorgung von digitalen Halbleiterschaltungen
DE3026951A1 (de) * 1980-07-16 1982-02-04 Siemens AG, 1000 Berlin und 8000 München Treiberstufe in integrierter mos-schaltkreistechnik mit grossem ausgangssignalverhaeltnis
US4456837A (en) * 1981-10-15 1984-06-26 Rca Corporation Circuitry for generating non-overlapping pulse trains

Also Published As

Publication number Publication date
DE3338206C2 (fr) 1990-02-08
GB2128832B (en) 1986-02-26
FR2535128A1 (fr) 1984-04-27
GB2128832A (en) 1984-05-02
IT8223869A0 (it) 1982-10-22
IT1210945B (it) 1989-09-29
DE3338206A1 (de) 1984-05-03
US4587441A (en) 1986-05-06
GB8328152D0 (en) 1983-11-23

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Legal Events

Date Code Title Description
D6 Patent endorsed licences of rights
ST Notification of lapse