FR2462779A1 - METHOD OF MANUFACTURING VMOS TRANSISTORS - Google Patents

Abstract

METHOD OF MANUFACTURING VMOS TRANSISTORS CONSISTING OF A HIGHLY DOPED SUBSTRATE FORMING DRAIN, FOR EXAMPLE OF TYPE N (1) FOR A VERTICAL N-CHANNEL TRANSISTOR, WITH AN N EPITAXIAL LAYER (2) IN WHICH ARE DIFFUSED TWO COMPLEMENTARY REGIONS N ( 6) AND P (5) FORMING WITH LAYER 2 A VERTICAL NPN STRUCTURE WHICH IS CROSSED BY A V-THROUGH CARRYING THE METAL GRID AND ITS ISOLATION LAYER AND WHOSE DIFFUSED REGIONS 6, 5 ARE CONNECTED BY THE SOURCE CONTACT. ACCORDING TO THE INVENTION THE COMPLEMENTARY REGIONS ARE SIMULTANEOUSLY FORMED BY A MIXTURE OF N AND P DOPANTS OF WHICH ONE HAS A LARGER DIFFUSION CONSTANT (P IN THE CASE OF THE N-CHANNEL VERTICAL TRANSISTOR). A SECOND THROAT 7 NOT REACHING THE EPITAXIAL LAYER IS MADE AT THE SAME TIME AS THE GRID THROAT 8 BY ATTACK THROUGH TWO WINDOWS OF DIFFERENT WIDTH BY MEANS OF AN ANISOTROPIC SOLUTION, THE SILICON HAVING THE 100 ORIENTATION. SOURCE 10 IS TAKEN THROUGH AN OPEN WINDOW IN THE THIN OXIDE LAYER COVERING THROATS 7 AND 8 AFTER THE GRID OXIDE DEPOSIT PHASE.

Description

The present invention relates to an improved and simplified method

  for the fabrication of VMOS transistors (metal-oxide-semiconductor field effect transistors with vertical structure) Conventional MOS transistors, as is well known, have a high conductive resistance and switching characteristics disadvantageous. The reason is the relative weakness of accuracy

  with which one can manufacture the structures of lateral transistors.

  The channel length, which determines the resistance in the conductive state, can not be accurately controlled. In addition, the extent of the part of the grid which covers the drain and the source results in high capacities and therefore in long switching times. Therefore, it is relatively difficult to obtain power MOS transistors

  and, more particularly, high frequency devices.

  For these reasons, the lateral structure has recently been replaced by a vertical structure, which has given rise to the known VMOS transistors (see "Nachrichten Electronik" 1 - 1978, pages 15 to 18, and "Electronik", 1977, n08, page 35). These have all the advantages of MOS transistors. They thus outweigh the bipolar transistors and even have

  higher switching speeds.

  The manufacturing processes of the bipolar transistors and the VMOS transistors are largely identical except for the chemical etching of the V-shaped groove and subsequent oxidation of the gate. Thus, the number of phases and the costs of

  VMOS process fabrication are higher than those of the bipolar process.

  The object of the invention is therefore to provide a method of

  making VMOS transistors both simplified and less expensive.

  This object is achieved by the invention in that a VMOS transistor consisting of a heavily doped substrate of a certain type of

  conductivity coated with an epitaxial layer of the same type of

  it itself covered with a layer of SiO 2 having a window through which is diffused in the epitaXial layer a region of the opposite conductivity type, the latter region in turn surrounding a diffused region of the same type of conductivity as the layer. epitaxin in which there is a V-shaped groove comprising the gate electrode, the drain contact being provided by the substrate and the

  source contact interconnecting the two conductivity type regions

  opposite, is manufactured by a method characterized in that the two opposite conductivity type regions are diffused simultaneously in the epitaxial layer 2 through the open window in the SiO 2 layer that two V-shaped grooves of different depths are etched by etching through an appropriate mask having two windows of different widths spaced apart from each other by a given minimum distance, after formation of a layer of SiO 2 which covers the grooves, the region to provide the source contact is exposed in the part of the SiO 2 layer covering the first groove, an aluminum layer is deposited by evaporation and the grid contact is obtained

  and the source contact by etching through a suitable mask.

  The invention will be better understood on reading the description

  detailed below, made by way of non-limiting example with reference to the appended figures 1 to 4, which represent: - Figures 1 to 3 the particular steps of the manufacturing method according to the invention, for the realization of an n-channel VMOS transistor; and FIG. 4 a vertical section of a p-channel VMOS transistor. In FIGS. 1 to 3, the support material is an n + type and orientation silicon substrate 1, so that the V-shaped grooves can be obtained by chemical etching in a self-restrictive manner in accordance with FIG. using anisotropic etching solutions. A

  layer 2 of n-type silicon is deposited by epitaxy on the substrate 1.

  On this layer 2, a layer 3 of SiO 2 is then formed by thermal oxidation. Then we open a window 4 in the layer 3 of SiO 2 by a

  photolithographic process. (see Figure 1).

  Through this window 4, the semiconductor washer is doped with a mixture of n and p type dopants. These dopants may be boron, arsenic or phosphorus. It must be ensured that, if a channel n is formed, the dopant constituting the p-type region has the greatest diffusion constant. In this case, boron and arsenic were chosen. The doping is followed by a diffusion phase, which gives a structure comprising a p-type region and an n-type region 6.

as shown in Figure 2.

  The next step is to form a V-shaped groove, not only for the gate contact, but also to interconnect the p-type region and the source contact. This is done using a mask with windows of widths

  different and spaced from each other by a given minimum distance.

  Then, the V-shaped grooves are chemically etched by employing an anisotropic etching solution. Because of the different widths of the windows, the edges of which are spaced apart on the paper plane by a distance equal to the width of the webs. throats in the shape of

  V, and by the use of both crystal orientation silicon

  lographic 100 and an anisotropic attack solution, different depths of attack are obtained; in addition, the chemical attack process is self-restrictive. In this way, a V-shaped deep groove 8 is formed for the gate contact and a shallower groove 7 for the connection between the source contact 10 and the p-type region 5. Together with the deposition of the gate oxide in the groove 8, a layer is deposited

  oxide protector in the groove 7, a part of this protective layer

  this being then removed during a photo-etching phase to open the contact of the source metallization. As a result, aluminum is deposited which is masked and etched to form the desired aluminum contacts in the source and gate regions, ie the source contact 10 and the gate contact 9 (Figure 3). The method according to the invention is illustrated in FIGS. 1 to 3 by the manufacture of an n-channel VMOS transistor. Of course, the same technique can also be used to make a p-channel VMOS transistor. In this case, the support material is a p + type substrate 11 (FIG. 4) on which a p-type layer 12 is epitaxially deposited, in which the n-type region 6 and the p-type region 5 are diffused. The n-type dopant must have a greater diffusion constant than the p-type dopant. Figure 4 shows a vertical section of a p-type VMOS transistor of this type, finished. Compared with conventional methods for manufacturing VMOS transistors, the method according to the present invention

  the advantage of saving a broadcast phase.

  It is obvious that the foregoing description has not been made

  as a non-limitative example, and that other variants may be

  envisaged without departing from the scope of the invention. -

-4-

Claims (2)

  1 - Method of manufacturing VMOS transistors consisting of a heavily doped substrate of a certain conductivity type covered with an epitaxial layer of the same conductivity type, itself covered with a SiO 2 layer comprising a window through which is diffused in the epitaxial layer a region of the opposite conductivity type, the latter region in turn surrounding a diffused region of the same conductivity type as the epitaxial layer in which there is a V-shaped groove comprising the gate electrode, the drain contact being provided by the substrate and the source contact interconnecting the two opposite conductivity type regions, characterized in that the two opposite conductivity type regions are simultaneously diffused in the epitaxial layer through the open window in the layer of SiO2, that two V-shaped grooves of different depths are dug by ch attack imique through a suitable mask having two windows of different widths spaced from each other by a given minimum distance, only after formation of a layer of SiO2 that covers the grooves, the region to provide the source contact is exposed in the part of the SiO 2 layer that covers the first groove, that an aluminum layer is deposited by evaporation and that the gate contact and the source contact are etched through an adequate mask.   2 - Method according to claim 1, characterized in that the dimensions of the open windows in the mask to obtain by etching the V-shaped grooves are chosen so that the second of these grooves comprising the gate contact penetrates in the epitaxial layer while the first groove penetrates only in the region of opposite conductivity type which covers the epitaxial layer.