GB2055247A - Method of fabricating VMOS transistors - Google Patents
Method of fabricating VMOS transistors Download PDFInfo
- Publication number
- GB2055247A GB2055247A GB8020113A GB8020113A GB2055247A GB 2055247 A GB2055247 A GB 2055247A GB 8020113 A GB8020113 A GB 8020113A GB 8020113 A GB8020113 A GB 8020113A GB 2055247 A GB2055247 A GB 2055247A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductivity type
- groove
- epitaxial layer
- vmos
- fabricating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims 1
- 238000001704 evaporation Methods 0.000 claims 1
- 239000002019 doping agent Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Element Separation (AREA)
Abstract
In a method of fabricating a VM0S transistor of the type in which the gate and source are disposed in a relatively deep V-groove (8) and a relatively shallow V-groove (7) respectively, the grooves (8, 7) are formed simultaneously by anisotropic etching through a mask having a large and a small window so disposed as to correspond with the position of the grooves. <IMAGE>
Description
SPECIFICATION
Method of fabricating VMOS transistors
The present invention relates to a method of fabricating VMOS transistors and to VMOS transistors fabricated by the method.
Conventional MOS field-effect transistors, as is well known, have a high ON resistance and an unfavourable switching behaviour. The reason is the relatively low accuracy with which lateral transistor structures can be fabricated. The channel length, which determines the ON resistance, cannot be precisely controlled.
Furthermore, the large portion of the gate overlapping the drain and source results in high capacitances and, consequently, long switching times. Therefore, power MOSFETs and particularly high-frequency devices are relatively difficult to realise.
For these reasons, the lateral structure has lately been replaced by a vertical structure, which has led to the known VMOS transistors (cf.
"Nachrichten Elektronik", 1~1978, pages 15 to 18, and "Elektronik", 1977, No. 8, page 35).
These transistors have all advantages of MOS field-effect transistors. They thus excel bipolar transistors and have even higher switching speeds than the latter.
Bipolar-transistor and VMOS-transistor fabrication processes are largely identical except for the etching of the V-shaped groove and the subsequent gate oxidation. Thus, the number of steps and the costs of the VMOS process are higher than those of the bipolar process.
Accordingly, the object of the invention is to provide a simplified, cost-reducing method of fabricating VMOS transistors.
According to the invention there is provided a method of fabricating a VMOS transistor of the type in which the gate and source are disposed in a relatively large V-groove and a relatively small Vgroove respectively, the method including etching said grooves simultaneously with an anisotropic etch through a mask having a relatively large window and a relatively small window, said windows being disposed in correspondence with the large and small grooves respectively.
The invention will now be explained in more detail with reference to the accompanying drawing, in which:
Figs. 1 to 3 illustrate the individual steps of the fabrication of an n-channel VMOS transistor, and
Fig. 4 shows a cross-section of a p-channel
VMOS transistor.
In Figs. 1 to 3, the supporting material in an n+ substrate 1 of (100)-oriented silicon, so that the
V-shaped grooves can be etched in a self-limiting manner using anisotropic etchants. An n-type silicon layer 2 is epitaxially deposited on the substrate 1. On the layer 2, an SiO2 layer 3 is then formed by thermal oxidation. A window 4 in the
SiO2 layer 3 is then opened by the photolithographic technique (see Fig. 1).
Through this window 4, the semiconductor wafer is doped with a mixture of n- and p-type dopants. The dopants may be boron, arsenic or phosphorus. Care should be taken to see that, if an n-channel is formed, the dopant resulting in the ptype region has the greater diffusion constant. In the present case boron and arsenic were chosen.
The doping is followed by a diffusion step, which gives a structure with a p-type region 5 and an ntype region 6, as shown in Fig. 2.
The next step is the formation of a V-shaped
groove, not only for the gate contact, but also to
interconnect the p-type region 5 and the source
contact. This is done with a mask containing windows of different width which are spaced a
given minimum distance apart. Then, the V
shaped grooves are etched using an anisotropic
etchant. By the different widths of the windows, whose edge spacing in the plane of the paper is
equal to the width of the V-shaped grooves, and
by the use of silicon of the crystallographic (100)order together with an anisotropic etchant, different depths of etching are obtained; in
addition, the etching process is self-limiting.
In this manner, a deep V-shaped groove 8 for the gate contact and a less deep V-shaped groove 7 for connecting the source contact 10 to the ptype region 5 are formed. Together with the deposition of the gate oxide 18 in the groove 8, a protective oxide layer is then deposited in the groove 7, a portion of which layer is then removed by a photoetch step to open the contact for the source metallisation. Subsequently, aluminium is deposited, masked, and etched to form the desired aluminium contacts in the source and gate areas, i.e., the source contact 10 and the gate contact 9 (Fig. 3). The method is illustrated in Figs. 1 to 3 by the fabrication of an n-channel VMOS transistor.
The same technique may also, of course, be used to fabricate a p-channel VMOS transistor. In that case, the supporting material is a p+ substrate 11 (Fig. 4), on which is deposited a p-type epitaxial layer 12, into which the n-type region 6 and the ptype region 5 are diffused. The n-type dopant must have a greater diffusion constant than the p-type dopant. A cross-section of such a finished pchannel VMOS transistor is shown in Fig. 4.
Compared to conventional VMOS processes, the method has the advantage that one diffusion step is saved.
Claims (5)
1. A method of fabricating a VMOS transistor of the type in which the gate and source are disposed in a relatively large V-groove and a relatively small V-groove respectively, the method including etching said grooves simultaneously with an anisotropic etch through a mask having a relatively large window and a relatively small window, said windows being disposed in correspondence with the large and small grooves respectively.
2. A method of fabricating VMOS transistors with a heavily doped substrate of one conductivity type and an overlying epitaxial layer of the same conductivity type, into which a region of opposite conductivity type is diffused through a window in a covering SiO2 layer, which region of opposite conductivity type, in turn, surrounds a diffused region of the conductivity type of the epitaxial layer, with a V-shaped groove extending into the epitaxial layer and containing the gate electrode, the drain contact being provided at the substrate, and the source contact interconnecting the two regions of opposite conductivity type, wherein the two regions of opposite conductivity type are diffused into the epitaxial layer through the window in the SiO2 layer at the same time, wherein V-shaped grooves of different depth are etched using a mask containing windows of different width which are spaced a given minimum distance apart, wherein after formation of the SiO2 layer covering the grooves, the area for the source contact is exposed in this SiO2 layer in the area of the groove, wherein an aluminium layer is deposited by evaporation, and wherein the gate contact and the source contact are etched using a mask.
3. A method as claimed in claim 2, wherein the dimensions of the windows in the mask for etching the V-shaped grooves are chosen so that the V-shaped groove containing the gate contact extends into the epitaxial layer, while the other Vshaped groove extends only into the region of opposite conductivity type overlying the epitaxial layer.
4. A method of fabricating VMOS transistors substantially as described herein with reference to the accompanying drawing.
5. A VMOS transistor made by a method as claimed in any one of claims 1 to 4.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2930780A DE2930780C2 (en) | 1979-07-28 | 1979-07-28 | Method of manufacturing a VMOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2055247A true GB2055247A (en) | 1981-02-25 |
| GB2055247B GB2055247B (en) | 1983-08-24 |
Family
ID=6077092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8020113A Expired GB2055247B (en) | 1979-07-28 | 1980-06-19 | Method of fabricating vmos transistors |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5621373A (en) |
| DE (1) | DE2930780C2 (en) |
| FR (1) | FR2462779A1 (en) |
| GB (1) | GB2055247B (en) |
| IE (1) | IE50027B1 (en) |
| IT (1) | IT1194673B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2165091A (en) * | 1984-09-27 | 1986-04-03 | Rca Corp | IGFET and method for fabricating same |
| US4748103A (en) * | 1986-03-21 | 1988-05-31 | Advanced Power Technology | Mask-surrogate semiconductor process employing dopant protective region |
| US4904613A (en) * | 1986-12-23 | 1990-02-27 | U.S. Philips Corporation | Method of manufacturing a DMOS device |
| EP0440394A2 (en) * | 1990-01-29 | 1991-08-07 | Motorola Inc. | Mosfet with substrate source contact |
| EP0459771A2 (en) * | 1990-05-31 | 1991-12-04 | Canon Kabushiki Kaisha | Electrode for semiconductor device and method for producing the same |
| EP0706223A1 (en) * | 1994-10-04 | 1996-04-10 | Siemens Aktiengesellschaft | Semiconductor device controlled by field effect |
| EP1005091A1 (en) * | 1998-11-17 | 2000-05-31 | STMicroelectronics S.r.l. | A method of manufacturing a vertical-channel MOSFET |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2076037B1 (en) * | 1970-01-12 | 1975-01-10 | Ibm | |
| US4219835A (en) * | 1978-02-17 | 1980-08-26 | Siliconix, Inc. | VMOS Mesa structure and manufacturing process |
-
1979
- 1979-07-28 DE DE2930780A patent/DE2930780C2/en not_active Expired
-
1980
- 1980-06-19 GB GB8020113A patent/GB2055247B/en not_active Expired
- 1980-06-25 JP JP8529480A patent/JPS5621373A/en active Pending
- 1980-07-23 FR FR8016208A patent/FR2462779A1/en active Granted
- 1980-07-24 IE IE1543/80A patent/IE50027B1/en unknown
- 1980-07-28 IT IT23733/80A patent/IT1194673B/en active
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2165091A (en) * | 1984-09-27 | 1986-04-03 | Rca Corp | IGFET and method for fabricating same |
| US4748103A (en) * | 1986-03-21 | 1988-05-31 | Advanced Power Technology | Mask-surrogate semiconductor process employing dopant protective region |
| US4904613A (en) * | 1986-12-23 | 1990-02-27 | U.S. Philips Corporation | Method of manufacturing a DMOS device |
| EP0440394A2 (en) * | 1990-01-29 | 1991-08-07 | Motorola Inc. | Mosfet with substrate source contact |
| EP0440394A3 (en) * | 1990-01-29 | 1992-01-29 | Motorola Inc. | Mosfet with substrate source contact |
| US5583075A (en) * | 1990-05-13 | 1996-12-10 | Canon Kabushiki Kaisha | Method for producing a semiconductor device with a particular source/drain and gate structure |
| EP0459771A2 (en) * | 1990-05-31 | 1991-12-04 | Canon Kabushiki Kaisha | Electrode for semiconductor device and method for producing the same |
| EP0459771A3 (en) * | 1990-05-31 | 1992-02-05 | Canon Kabushiki Kaisha | Electrode for semiconductor device and method for producing the same |
| US5378914A (en) * | 1990-05-31 | 1995-01-03 | Canon Kabushiki Kaisha | Semiconductor device with a particular source/drain and gate structure |
| EP0706223A1 (en) * | 1994-10-04 | 1996-04-10 | Siemens Aktiengesellschaft | Semiconductor device controlled by field effect |
| EP1005091A1 (en) * | 1998-11-17 | 2000-05-31 | STMicroelectronics S.r.l. | A method of manufacturing a vertical-channel MOSFET |
| US6362025B1 (en) | 1998-11-17 | 2002-03-26 | Stmicroelectronics S.R.L | Method of manufacturing a vertical-channel MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2055247B (en) | 1983-08-24 |
| FR2462779B3 (en) | 1982-04-02 |
| IE50027B1 (en) | 1986-02-05 |
| DE2930780C2 (en) | 1982-05-27 |
| DE2930780A1 (en) | 1981-01-29 |
| FR2462779A1 (en) | 1981-02-13 |
| IE801543L (en) | 1981-01-28 |
| IT8023733A0 (en) | 1980-07-28 |
| JPS5621373A (en) | 1981-02-27 |
| IT1194673B (en) | 1988-09-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |