FR2449945A1 - Bloc logique pour circuits numeriques integres - Google Patents

Bloc logique pour circuits numeriques integres

Info

Publication number
FR2449945A1
FR2449945A1 FR8001320A FR8001320A FR2449945A1 FR 2449945 A1 FR2449945 A1 FR 2449945A1 FR 8001320 A FR8001320 A FR 8001320A FR 8001320 A FR8001320 A FR 8001320A FR 2449945 A1 FR2449945 A1 FR 2449945A1
Authority
FR
France
Prior art keywords
logic block
register
digital circuits
cells
integrated digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8001320A
Other languages
English (en)
French (fr)
Other versions
FR2449945B1 (en:Method
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of FR2449945A1 publication Critical patent/FR2449945A1/fr
Application granted granted Critical
Publication of FR2449945B1 publication Critical patent/FR2449945B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
FR8001320A 1979-01-23 1980-01-22 Bloc logique pour circuits numeriques integres Granted FR2449945A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19792902375 DE2902375C2 (de) 1979-01-23 1979-01-23 Logikbaustein für integrierte Digitalschaltungen

Publications (2)

Publication Number Publication Date
FR2449945A1 true FR2449945A1 (fr) 1980-09-19
FR2449945B1 FR2449945B1 (en:Method) 1985-03-01

Family

ID=6061148

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8001320A Granted FR2449945A1 (fr) 1979-01-23 1980-01-22 Bloc logique pour circuits numeriques integres

Country Status (4)

Country Link
JP (1) JPS55129772A (en:Method)
DE (1) DE2902375C2 (en:Method)
FR (1) FR2449945A1 (en:Method)
GB (1) GB2041546B (en:Method)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5618766A (en) * 1979-07-26 1981-02-21 Fujitsu Ltd Testing apparatus for logic circuit
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
JPS5789154A (en) * 1980-11-25 1982-06-03 Nec Corp Logical integrated circuit
JPS57106218A (en) * 1980-12-23 1982-07-02 Fujitsu Ltd Cmos type dff circuit
US4551838A (en) * 1983-06-20 1985-11-05 At&T Bell Laboratories Self-testing digital circuits
US4680539A (en) * 1983-12-30 1987-07-14 International Business Machines Corp. General linear shift register
EP0196171B1 (en) * 1985-03-23 1991-11-06 International Computers Limited Digital integrated circuits
GB2178175A (en) * 1985-07-18 1987-02-04 British Telecomm Logic testing circuit
JPH07122653B2 (ja) * 1986-04-21 1995-12-25 ソニー株式会社 試験回路
JP2508427B2 (ja) * 1986-09-11 1996-06-19 ソニー株式会社 Ｉｃ回路
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure
US4870346A (en) * 1987-09-14 1989-09-26 Texas Instruments Incorporated Distributed pseudo random sequence control with universal polynomial function generator for LSI/VLSI test systems
JPH01155281A (ja) * 1987-12-11 1989-06-19 Nec Corp 論理テスト回路
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
DE19604375C2 (de) * 1996-02-07 1999-04-29 Martin Kuboschek Verfahren zur Auswertung von Testantworten zu prüfender digitaler Schaltungen und Schaltungsanordnung zur Durchführung des Verfahrens

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON COMPUTERS, vol. C-24, no. 5, mai 1975, pages 489-497, New York, US *

Also Published As

Publication number Publication date
DE2902375A1 (de) 1980-07-31
JPH0225155B2 (en:Method) 1990-05-31
GB2041546A (en) 1980-09-10
GB2041546B (en) 1983-04-07
FR2449945B1 (en:Method) 1985-03-01
DE2902375C2 (de) 1984-05-17
JPS55129772A (en) 1980-10-07

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Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse