GB2178175A - Logic testing circuit - Google Patents
Logic testing circuit Download PDFInfo
- Publication number
- GB2178175A GB2178175A GB08518132A GB8518132A GB2178175A GB 2178175 A GB2178175 A GB 2178175A GB 08518132 A GB08518132 A GB 08518132A GB 8518132 A GB8518132 A GB 8518132A GB 2178175 A GB2178175 A GB 2178175A
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- United Kingdom
- Prior art keywords
- register
- flip
- circuit
- flops
- input
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A logic testing circuit comprises a plurality of flip-flops (22-26) forming a shaft register, predetermined ones of the flip-flops having inversion means (8, 7) connected to them such that after asserting a logical value (O) at the input (S) to the register whilst clocking it through the register a predetermined digital word (11010) may be output from parallel outputs of the flip-flops. The circuit may also comprise a circuit for generating a plurality of digital words and control means, operable to connect either the latter circuit or the logical value to the input of the register. A plurality of such circuits may be used to pseudo-exhaustively test a circuit by using one register to which a single logical value is applied to provide a sensitising vector for one part of a circuit whilst an exhaustive test is applied to another part of the circuit through another such register. The connections may then be reversed to complete the test. <IMAGE>
Description
SPECIFICATION
Logic circuit
This invention relates to circuits and particularly to a circuit for use in a register for the self testing of integrated circuits.
The complexity of currently available integrated circuits requires the use of equally complex inspection and test procedures during their manufacture and use. Such tests in general comprise providing a known set of inputs to a circuit and then comparing the outputs produced with a known good set of outputs derived from a simulation or a known good circuit. In order to reduce the complexity of the external test equipment required to test such circuits it has become common to build test circuitry into integrated circuits in order to make the circuits self testing and reduce the complexity of the task of generating a test procedure for a circuit.Such self test methods are commonly used in circuits using both combinational logic and stored state devices where it is helpful to be able to predetermine the state of the stored state devices before a test is carried out and to analyse the state of the stored state devices after a test. In order to be able to do this it is known to provide a scan design circuit which enables the stored state devices to be preset before and read after a test is conducted by using a circuit involving one or more scan path shift registers which enable the preset values to be scanned into the circuit before the test and scanned out afterwards.
A number of different testing techniques using scan path circuits are known one particular form using a design known as level sensitive scan design. However in order to make the circuit self testing it is necessary to provide some way of generating the test vectors to be scanned into the circuit. One way in which this can be done is by using a linear feedback shift register (LFSR) with a predetermined set of feedback connections in order to generate the test patterns which are to be fed into the scan registers of a scan design logic circuit.
The use of LFSRs can be utilised for this basic purpose in a number of different ways. The
LFSR may be a separate circuit from the scan path shift register if desired. However, one particular known circuit which can be used to fulfil a number of functions in such a self test circuit is one using a technique known as built in logic block observation (BILBO). In a circuit using such a technique (known as a BILBO) the circuit may operate in a number of different modes according to the signals present on it's control lines. It is thus able to function in both an LFSR mode and a scan path mode.
Whichever form of scan design circuit is used the circuit to be tested is subjected to a substantially exhaustive set of tests generated
by the LFSR which is enabled to produce an effectively exhaustive test by careful selection of the LFSR feedback taps. This is perfectly adequate in most situations. In some combinational logic circuits though a large subset of inputs may determine any particular output; such a circuit is said to have a wide logic cone. However, in circuits involving very wide logic cones involving many possible input patterns if the tests to be conducted are to be exhaustive the number of test patterns required is prohibitive in terms of the time required to conduct the tests. In fact the number of vectors required to test a circuit increases exponentially with the width of the cone.However the number of useful vectors, namely those forming the 100% single stuck fault test set, increases approximately linearly with cone size. Horeover, the proportion of large cones, while varying from one design to another, is usually small so that a very small area of the circuit may be responsible for a very large increase in test time which may be large for this serial test method. Various solutions to this problem have been proposed.
One method is to generate conventional predetermined test vectors which can be used in conjunction with exhaustive tests of other parts of the circuit to be tested. However, this is incompatible with existing self test methods in that it would require storage of such test patterns on the chip to be tested in ROM or some other storage means if the chip were to be self testing. If cones of a size greater than some predetermined limit were banned from circuits altogether the problem would also be solved, though in doing so serious constraints would be placed on systems designers.
According to the present invention there is provided a logic testing circuit comprising a shift register comprising a plurality of flip-flops connected in series for output of a predetermined digital word, means operable tc assert a predetermined logical value at the input to said shift register and for clocking it through each flip-flop of said register, predetermined ones of said flip-flops of said register having inversion means connected to them such that after asserting said logical value at the input to said register whilst clocking it through each flip-flop of said register said predetermined digital word may be output from parallel outputs of said flip-flops.Such a logic circuit is able to effectively store a predetermined test vector without the function of the shift register as a scan register being affected and yet is com
patible with existing self test methods and does not require additional ROM storage in order to be able to output predetermined test vectors. The inverse of the predetermined logical value may be used in order to be able to output the inverse of the predetermined digital word. Furthermore it is also possible to use a
plurality of predetermined logical values to output an additional predetermined word to that produced by the assertion of a logical value. In this case a generator of a simple sequence of logical values might be used for example a flip flop arranged to produce an alternate sequence of logical values and their inverses.
Preferably the logic testing circuit further comprises a test generating circuit for generating a plurality of digital words and control means operable to connect either the output of said test generating circuit or said means for asserting said logical value to the input of said register. Such an arrangement allows easy testing using either a predetermined vector or a substantiaUy exhaustive set of test vectors.
In one embodiment of the present invention the logic circuit may be for forming a scan path register wherein said flip-flops have data path and scan path inputs and outputs, said inversion means comprise NOT gates connected between predetermined flip-flops and their data path outputs and said predetermined flip-flops are provided with NOT gates connected between them and their data path inputs.
In another preferred embodiment of the present invention the plurality of flip-flops connected in series are for storage and output of said predetermined digital word and said inversion means are for applying the inverse of the logical values applied to the inputs of said predetermined ones of said flip-flops to the input of respective adjacent flip-flops such that asserting said logical value at the input to said register and clocking said value through each flip-flop of said register stores said digital word in said register. Such an embodiment of the present invention reduces the number of extra components required to convert a prior art scan path shift register to one according to the present invention.
In either embodiment each of said inversion means may comprise a NOT gate connected between the output of a flip-flop and the input of the adjacent flip-flop Alternatively said predetermined ones of said flip-flops of said register have a normal output and a complementary output whose logical value is the inverse of the now al output and said inversion means comprise connections between the complementary outputs of said predetermined flip-flops and the inputs of respective adjacent flip-flops in said register. Using such an arrangement minimises the extra components required in addition to those ordinarily used in scan register circuits.
The shift register used in a logic circuit according to the present invention may form part of a linear feedback shift register, a scan path shift register or part of a built in logic block observation register circuit which is capable of fulfilling both of the latter functions at least, depending on the control signals supplied to it. Since the circuit according to the present invention uses few extra components
it is easily used in such embodiments in exist
ing designs of self testing ciruits.
In a further preferred embodiment of the
present invention there is provided an inte
grated circuit comprising a plurality of circuits according to the present invention, parallel outputs of the the flip-flops of each circuit being connected to a respective set of the inputs of a logic circuit to be tested. Such an arrangement enables an integrated circuit to
be self testing whilst using a method of testing in which large cones are split for the purpose of testing. One part of a cone may be sensitised by a fixed set of input values determined by an appropriate shift register according to the present invention having an appropriate single logical value assserted at its input whilst clocking occurs, whilst the rest of the cone may be tested substantially exhaustively by use of a linear feedback shift register.Preferably the test method comprises the steps of selecting a logic cone in the circuit to be tested, dividing the inputs to said logic cone into at least two subsets connecting the parallel outputs of the flip-flops of respective circuits according to the present invention to each subset of inputs asserting a logical value at the input to a first one of said registers so as to apply a predetermined set of logical test values to one of said subset of inputs and applying the output of said test generating circuit to the other of said registers so as to apply a substantially exhaustive set of logical test values to the other of said subset of inputs and then applying said exhaustive set of test values to at least said first register whilst asserting a single logical value at the input to the other of said registers.
Embodiments of the present invention will now be described in further detail with reference to the accompanying drawings in which:
Figure 1 shows a logic circuit according to the prior art comprising a shift register comprising a plurality of flip-flops.
Figure 2 shows a logic circuit according to a first embodiment of the present invention using NOT gates between selected flip-flops and their parallel outputs.
Figure 3 shows a logic circuit according to a further embodiment of the present invention using NOT gates between selected adjacent flip-flops.
Figure 4 shows a logic circuit according to a further embodiment of the present invention using connections between the complementary outputs of selected adjacent flip-flops and the inputs of adjacent flip-flops.
Figure 5 shows a BILBO incorporating a logic circuit according to an embodiment of the present invention.
Figure 6 shows a logic circuit a part of which is undergoing a deterministic test and another part of which is undergoing an exhaustive test.
Figure 7 shows in diagrammatic form a cir cuit for carrying out tests such as that shown in figure 6.
Figure 8 shows in tabular form the tests and scan register inputs for the circuit shown in figure 7.
In figure 1 there is shown a shift register (1) comprising a number of flip-flops (2, 3, 4, 5, 6, ) connected in series. Such a shift register might be used as a scan path register or incorporated with suitable modifications into a linear feedback shift register or BILBO element.
The normal output, (designated Q) of each flip-flop in the shift register is fed to the input of the next flip-flop in the register. The value or values input to the register thus define the contents of the shift register and if the input is held at a logical value of 0 and the value clocked through the register each stage of the register will eventually contain 0 as well. It is thus necessary if the register is to be used to sensitise or deterministically test a circuit to which it is connected to store the sensitising or deterministic test vector in ROM memory so that it may be accessed when required even if exhaustive tests may be carried out by feeding the register from a linear feedback shift register.
In figure 2 a first embodiment of the present invention forming a scan path register is shown using NOT gates (7) between selected flip-flops (22, 23, 25) and their scan path parallel outputs. On the data path inputs of the flip-flops having NOT gates on their scan path outputs further corresponding NOT gates (8) are provided in order to allow the data paths to operate normally when the shift register is not being used in a scan path mode. The result of such an arrangement is that the register may be used quite normally as a scan path register since the register is then required to have an exhaustive set of test inputs fed through it and read from it in parallel. However when it is required to sensitise a part of a circuit or deterministically test it using a particular vector all that is required is the assertion of a single logical value at the input to the shift register.When this is done and the value is clocked through the register the register will thereafter have stored in it a vector which when read in parallel via the inversion means, which may be NOT gates, will be the desired test vector. There is thus no need for the storage of any sensitising or deterministic test vectors in ROM and the vector may be effectively stored by the presence of inverters for example NOT gates on the appropriate parallel flip-flop outputs. Two sensitising or deterministic test vectors may in fact be effectively stored the one being the inverse of the other since either a '1' or a '0' may be asserted at the input to the shift register.
In figure 3 a preferred embodiment of the present invention is shown using NOT gates (9) between selected adjacent flip-flops (32, 33) (33, 34) (35, 36). The parallel outputs of the flip-flops may be taken from either the input (11) or the output (10) of the NOT gates. In the latter case though the data path input to the flip flop concerned will as shown in figure 2 require a further NOT gate on the data path input to allow the data paths to operate normally when the shift register is not being used in a scan path mode. In this manner the parallel output of the shift register after a single logical value has been clocked through it may be determined by the presence or absence of an inversion means, which may be a NOT gate, between the output of a flipflop and the next flip-flop in the register.It is preferred if the data path can be kept free of inversion means in order to avoid the possibility of a timing penalty caused by the need for two inversions in the data path when inversion means are used in the data path output rather than inbetween the flipflops in only the scan path.
In figure 4 a further preferred embodiment of the present invention is shown using connections between the complementary outputs (12) of selected flip-flops and the inputs of adjacent flip-flops (43, 44) (44, 45) (45, 46).
This is a particularly advantageous arrangement of such a shift register since not only is the need for inversion means in the data path avoided but no additional components are required if flip-flops having both a normal and a complementary output are used in the construction of the shift register. The output of the shift register when a single logical value is asserted at the input to the shift register and clocked through it is determined by whether the connections between the adjacent flipflops are taken from the normal or complementary output of the previous flip-flop in the register.
In figure 5 a BILBO incorporating a logic circuit according to an embodiment of the present invention is shown. When 'O' is asserted on control line A (10) and '1' on control line
B (11) the BILBO element shown acts as a scan path shift register when the multiplexer selects the scan data in (SDI) input. However by arranging for the inputs of some of these inverters to be taken from the complementary outputs (12) of certain predetermined flip-flops (53,54,55) in the shift register the BILBO can be arranged to store a predetermined test vector when a single logical value is asserted at the input to the register and clocked through it. This modification to an existing
BILBO element does not in any way affect its ability to function normally in its other modes as a linear feedback shift register, a latch or in a reset mode for example.
In figure 6 a logic circuit is shown a part of which is shown with a sensitising vector being applied to a subset of inputs (17) and another part of which is undergoing an exhaustive test (18). This shows schematically how a logic circuit comprising a very wide logic cone may be tested more easily by using a 'divide and conquer' technique in which the circuit inputs are divided into two or more groups one of which is sensitised using a predetermined input test vector whilst the other is tested exhaustively. The process is then reversed so that each part of the circuit will have been tested exhaustively. Preferably the cardinality of the input subsets is arranged to be approximately equal in order to reduce the time taken for testing to a minimum.This form of pseudo-exhaustive test is difficult to arrange with existing designs of self test circuits since the sensitising test vectors must be stored separately in ROM which requires further circuitry. However using a logic circuit according to the present invention it is possible to use such a technique without the need for separate storage means for the sensitising test vectors. In figure 7 there is shown in diagrammatic form a circuit which uses level sensitive scan design (LSSD) to test a logic circuit having a very wide logic cone in it.At least two scan registers (13, 14) are provided which are supplied with test vectors from a linear feedback shift register (15) via a selection means which feeds the appropriate output of the
LFSR to the appropriate scan register (it is possible to utilise only one scan register if the sensitising test vectors are common to both subsets of inputs and a multiplexing device is used). The output from the scan registers is then analysed in the analysis means (16). As shown in figure 8 the inputs to the scan registers may be arranged to carry out a number of different tests so that the circuit pseudoexhaustively tests different parts of the circuit or acts as a conventional LSSD ciruit or initialises itself.Since either '0' or '1' may be asserted at the input to the scan registers according to the present invention there are two possible deterministic test vectors which may be applied to each subset of circuit inputs as is shown by tests 1A/1B and 2A/2B. It is possible in applying the test scheme that the circuits to be tested will have wide logic cones which overlap. In such a case it is preferable that the sensitising test vectors have as many 'don't care' states (X) as possible and that assignments are made to latches which only drive one wide cone. It is possible however to use shift registers according to the present invention to produce more than one or two predetermined sensitising test vectors by arranging a means for asserting a predetermined sequence of logical values at the input to the shift register which, taking the inter stage inversions or output inversions into account, will enable the output of a different predetermined word to that output following the assertion of a single logical value at the shift register input. The means for asserting a predetermined sequence of logical values may be quite simple and only comprise, for example, a means for producing a string of alternate logical values and their inverses. The sensitising test vectors for a circuit may be determined by a suitable algorithm similiar to a line justification algorithm.
Claims (13)
1. A logic testing circuit comprising a shift register comprising a plurality of flip-flops connected in series for output of a predetermined digital word, means operable to assert a predetermined logical value at the input to said shift register and for clocking it through each flip-flop of said register, predetermined ones of said flip-flops of said register having inversion means connected to them such that after asserting said logical value at the input to said register whilst clocking it through each flip-flop of said register said predetermined digital word may be output from parallel outputs of said flip-flops.
2. A logic testing circuit according claim 1 further comprising a test generating circuit for generating a plurality of digital words and control means operable to connect either the output of said test generating circuit or said means for asserting said logical value to the input of said register.
3. A logic circuit according to claim 1 or claim 2 for forming a scan path register wherein said flip-flops have data path and scan path inputs and outputs, said inversion means comprise NOT gates connected between predetermined flip-flops and their data path outputs and said predeternined flip-flops are provided with NOT gates connected between them and their data path inputs.
4. A logic circuit according to claim 1 or claim 2 wherein said plurality of flip-flops connected in series are for storage and output of said predetermined digital word and said inversion means are for applying the inverse of the logical values applied to the inputs of said predetermined ones of said flip-flops to the input of respective adjacent flip-flops such that asserting said logical value at the input to said register and clocking said value through each flip-flop of said register stores said digital word in said register.
5. A logic circuit according to claim 3 or claim 4 wherein each of said inversion means comprises a NOT gate connected between the output of a flip-flop and the input of the adjacent flip-flop.
6. A logic circuit according to claim 4 wherein said predetermined ones of said flipflops of said register have a normal output and a complementary output whose logical value is the inverse of the normal output and said inversion means comprise connections between the complementary outputs of said predetermined flip-flops and the inputs of respective adjacent flip-flops in said register.
7. A logic circuit according to any one of the preceding claims wherein said shift register forms part of a linear feedback shift regis ter.
8. A logic circuit according to any one of the preceding claims wherein said shift register forms part of a scan path shift register
9. A logic circuit according to claim 7 or 8 wherein said shift register forms part of a built in logic block observation register circuit.
10. An integrated circuit comprising a plural~ ity of circuits according to any one of the preceding claims parallel outputs of the flipflops of each circuit being connected to a respective set of the inputs of a logic cone of a logic circuit to be tested.
11. A method of testing a digital circuit comprising the steps of selecting a logic cone in said circuit to be tested, dividing the inputs to said logic cone into at least two subsets connecting the parallel outputs of the flip-flops of respective circuits according to any one of claims 2 to 9 to each subset of inputs asserting a logical value at the input to a first one of said registers so as to apply a predetermined set of logical test values to one of said subset of inpu;s and applying the output of said test generating circuit to the other of said registers so as to apply a substantially exhaustive set of logical test values to the other of said subset of inputs and then applying said exhaustive set of test values to at least said first register whilst asserting a single logical value at the input to the other of said registers.
12. A circuit substantially as described herein with reference to the accompanying drawings 2 to 8.
13. A method of testing a circuit substantially as described herein with reference to the accompanying drawings 2 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08518132A GB2178175A (en) | 1985-07-18 | 1985-07-18 | Logic testing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08518132A GB2178175A (en) | 1985-07-18 | 1985-07-18 | Logic testing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8518132D0 GB8518132D0 (en) | 1985-08-21 |
| GB2178175A true GB2178175A (en) | 1987-02-04 |
Family
ID=10582459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08518132A Withdrawn GB2178175A (en) | 1985-07-18 | 1985-07-18 | Logic testing circuit |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2178175A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1355706A (en) * | 1970-07-17 | 1974-06-05 | Philips Electronic Associated | Device comprising a plurality of series arranged storage elements |
| GB1421038A (en) * | 1972-02-29 | 1976-01-14 | Tokyo Shibaura Electric Co | Apparatus for fixing the levels of outputs from a data storing circuit |
| US4066882A (en) * | 1976-08-16 | 1978-01-03 | Grumman Aerospace Corporation | Digital stimulus generating and response measuring means |
| GB2041546A (en) * | 1979-01-23 | 1980-09-10 | Mucha J | Logic module or logic means for or in an integrated digital circuit |
| GB1599157A (en) * | 1976-12-24 | 1981-09-30 | Indep Broadcasting Authority | Digital recognition circuits |
| EP0037965A2 (en) * | 1980-04-11 | 1981-10-21 | Siemens Aktiengesellschaft | Device for testing a digital circuit with test circuits enclosed in this circuit |
-
1985
- 1985-07-18 GB GB08518132A patent/GB2178175A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1355706A (en) * | 1970-07-17 | 1974-06-05 | Philips Electronic Associated | Device comprising a plurality of series arranged storage elements |
| GB1421038A (en) * | 1972-02-29 | 1976-01-14 | Tokyo Shibaura Electric Co | Apparatus for fixing the levels of outputs from a data storing circuit |
| US4066882A (en) * | 1976-08-16 | 1978-01-03 | Grumman Aerospace Corporation | Digital stimulus generating and response measuring means |
| GB1599157A (en) * | 1976-12-24 | 1981-09-30 | Indep Broadcasting Authority | Digital recognition circuits |
| GB2041546A (en) * | 1979-01-23 | 1980-09-10 | Mucha J | Logic module or logic means for or in an integrated digital circuit |
| EP0037965A2 (en) * | 1980-04-11 | 1981-10-21 | Siemens Aktiengesellschaft | Device for testing a digital circuit with test circuits enclosed in this circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8518132D0 (en) | 1985-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |