FR2447095B1 - Procede pour la fabrication de transistors mos complementaires a integration poussee pour tensions elevees - Google Patents

Procede pour la fabrication de transistors mos complementaires a integration poussee pour tensions elevees

Info

Publication number
FR2447095B1
FR2447095B1 FR8001303A FR8001303A FR2447095B1 FR 2447095 B1 FR2447095 B1 FR 2447095B1 FR 8001303 A FR8001303 A FR 8001303A FR 8001303 A FR8001303 A FR 8001303A FR 2447095 B1 FR2447095 B1 FR 2447095B1
Authority
FR
France
Prior art keywords
manufacture
high voltages
complementary transistors
integrated mos
push integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8001303A
Other languages
English (en)
French (fr)
Other versions
FR2447095A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
ATES Componenti Elettronici SpA
SGS ATES Componenti Elettronici SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATES Componenti Elettronici SpA, SGS ATES Componenti Elettronici SpA filed Critical ATES Componenti Elettronici SpA
Publication of FR2447095A1 publication Critical patent/FR2447095A1/fr
Application granted granted Critical
Publication of FR2447095B1 publication Critical patent/FR2447095B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
FR8001303A 1979-01-22 1980-01-22 Procede pour la fabrication de transistors mos complementaires a integration poussee pour tensions elevees Expired FR2447095B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT19484/79A IT1166587B (it) 1979-01-22 1979-01-22 Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate

Publications (2)

Publication Number Publication Date
FR2447095A1 FR2447095A1 (fr) 1980-08-14
FR2447095B1 true FR2447095B1 (fr) 1985-11-22

Family

ID=11158410

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8001303A Expired FR2447095B1 (fr) 1979-01-22 1980-01-22 Procede pour la fabrication de transistors mos complementaires a integration poussee pour tensions elevees

Country Status (5)

Country Link
US (1) US4277291A (enExample)
DE (1) DE3002051A1 (enExample)
FR (1) FR2447095B1 (enExample)
GB (1) GB2047464B (enExample)
IT (1) IT1166587B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0020144B1 (en) * 1979-05-31 1986-01-29 Fujitsu Limited Method of producing a semiconductor device
NL8003612A (nl) * 1980-06-23 1982-01-18 Philips Nv Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd door toepassing van deze werkwijze.
US4345366A (en) * 1980-10-20 1982-08-24 Ncr Corporation Self-aligned all-n+ polysilicon CMOS process
FR2507013A1 (fr) * 1981-06-02 1982-12-03 Efcis Procede de separation entre composants elementaires dans un circuit integre et application a une structure de transistors cmos
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4528581A (en) * 1981-10-21 1985-07-09 Hughes Aircraft Company High density CMOS devices with conductively interconnected wells
US4426766A (en) * 1981-10-21 1984-01-24 Hughes Aircraft Company Method of fabricating high density high breakdown voltage CMOS devices
US4435896A (en) 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
US4422885A (en) * 1981-12-18 1983-12-27 Ncr Corporation Polysilicon-doped-first CMOS process
US4613885A (en) * 1982-02-01 1986-09-23 Texas Instruments Incorporated High-voltage CMOS process
US4442591A (en) * 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
US4450021A (en) * 1982-02-22 1984-05-22 American Microsystems, Incorporated Mask diffusion process for forming Zener diode or complementary field effect transistors
US4435895A (en) 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
IT1210872B (it) * 1982-04-08 1989-09-29 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
US4474624A (en) * 1982-07-12 1984-10-02 Intel Corporation Process for forming self-aligned complementary source/drain regions for MOS transistors
US4480375A (en) * 1982-12-09 1984-11-06 International Business Machines Corporation Simple process for making complementary transistors
US4476621A (en) * 1983-02-01 1984-10-16 Gte Communications Products Corporation Process for making transistors with doped oxide densification
EP0123384A1 (en) * 1983-02-25 1984-10-31 Western Digital Corporation Complementary insulated gate field effect integrated circuit structure and process for fabricating the structure
US4471523A (en) * 1983-05-02 1984-09-18 International Business Machines Corporation Self-aligned field implant for oxide-isolated CMOS FET
US4574467A (en) * 1983-08-31 1986-03-11 Solid State Scientific, Inc. N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel
US4717683A (en) * 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US5292671A (en) * 1987-10-08 1994-03-08 Matsushita Electric Industrial, Co., Ltd. Method of manufacture for semiconductor device by forming deep and shallow regions
GB2237445B (en) * 1989-10-04 1994-01-12 Seagate Microelectron Ltd A semiconductor device fabrication process
US5328866A (en) * 1992-09-21 1994-07-12 Siliconix Incorporated Low temperature oxide layer over field implant mask
US5439842A (en) * 1992-09-21 1995-08-08 Siliconix Incorporated Low temperature oxide layer over field implant mask
US5372955A (en) * 1993-08-02 1994-12-13 United Microelectronics Corporation Method of making a device with protection from short circuits between P and N wells
US5525535A (en) * 1995-07-26 1996-06-11 United Microelectronics Corporation Method for making doped well and field regions on semiconductor substrates for field effect transistors using liquid phase deposition of oxides
US5861330A (en) * 1997-05-07 1999-01-19 International Business Machines Corporation Method and structure to reduce latch-up using edge implants
KR100272176B1 (ko) * 1998-09-30 2000-12-01 김덕중 Bicdmos 소자의 제조방법
KR101800783B1 (ko) * 2016-10-14 2017-11-23 서강대학교 산학협력단 실리콘 카바이드 기반의 트랜지스터 및 이를 제조하는 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3750268A (en) * 1971-09-10 1973-08-07 Motorola Inc Poly-silicon electrodes for c-igfets
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
GB1503017A (en) * 1974-02-28 1978-03-08 Tokyo Shibaura Electric Co Method of manufacturing semiconductor devices
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
US4135955A (en) * 1977-09-21 1979-01-23 Harris Corporation Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation
US4149915A (en) * 1978-01-27 1979-04-17 International Business Machines Corporation Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions

Also Published As

Publication number Publication date
US4277291A (en) 1981-07-07
IT1166587B (it) 1987-05-05
GB2047464B (en) 1983-05-25
FR2447095A1 (fr) 1980-08-14
IT7919484A0 (it) 1979-01-22
GB2047464A (en) 1980-11-26
DE3002051C2 (enExample) 1989-02-02
DE3002051A1 (de) 1980-07-31

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