FR2419564A1 - Dispositif de controle de memoire - Google Patents

Dispositif de controle de memoire

Info

Publication number
FR2419564A1
FR2419564A1 FR7905626A FR7905626A FR2419564A1 FR 2419564 A1 FR2419564 A1 FR 2419564A1 FR 7905626 A FR7905626 A FR 7905626A FR 7905626 A FR7905626 A FR 7905626A FR 2419564 A1 FR2419564 A1 FR 2419564A1
Authority
FR
France
Prior art keywords
memory
control device
memory control
read
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7905626A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fujitsu Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Fanuc Ltd filed Critical Fujitsu Fanuc Ltd
Publication of FR2419564A1 publication Critical patent/FR2419564A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Devices For Supply Of Signal Current (AREA)

Abstract

L'invention concerne l'informatique. Un dispositif de contrôle de mémoire fait intervenir une mémoire morte M divisée en blocs BL1, BL2,... Bln et un processeur CPU. La mémoire contient en outre des mots de contrôle A1, A2,... An qui correspondent à ses blocs respectifs. Pendant ses temps morts, le processeur contrôle la mémoire en comparant chaque mot de contrôle avec le résultat d'une opération effectuée sur les mots contenus dans le bloc correspondant. Application au contrôle des mémoires mortes.
FR7905626A 1978-03-06 1979-03-05 Dispositif de controle de memoire Withdrawn FR2419564A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2510678A JPS54117641A (en) 1978-03-06 1978-03-06 Memory inspecting system

Publications (1)

Publication Number Publication Date
FR2419564A1 true FR2419564A1 (fr) 1979-10-05

Family

ID=12156663

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7905626A Withdrawn FR2419564A1 (fr) 1978-03-06 1979-03-05 Dispositif de controle de memoire

Country Status (4)

Country Link
JP (1) JPS54117641A (fr)
DE (1) DE2906789A1 (fr)
FR (1) FR2419564A1 (fr)
GB (1) GB2016758B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105897A (en) * 1979-01-31 1980-08-13 Hitachi Koki Co Ltd Memory device
DE2939461C2 (de) * 1979-09-28 1989-07-20 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Feststellen von Datenstörungen in Speichern
JPS5683898A (en) * 1979-12-12 1981-07-08 Casio Comput Co Ltd Prom error detection system
JPS56101700A (en) * 1980-01-14 1981-08-14 Meidensha Electric Mfg Co Ltd Rom fault diagnostic system
JPS56147249A (en) * 1980-04-18 1981-11-16 Fujitsu Ltd Self-diagnostic processing system for unit made into firmware
US4442501A (en) * 1981-02-26 1984-04-10 Pitney Bowes Inc. Electronic postage meter with weak memory indication
JPS5812200A (ja) * 1981-07-13 1983-01-24 Fanuc Ltd メモリ検査方法
JPS59178695A (ja) * 1983-03-30 1984-10-09 Nittan Co Ltd 読出し専用メモリチエツク装置
JPS6030000A (ja) * 1983-07-27 1985-02-15 Mitsubishi Electric Corp 半導体メモリ装置
JPS62117651U (fr) * 1986-01-17 1987-07-25
DE4230615C2 (de) * 1992-09-12 2002-05-08 Bosch Gmbh Robert Verfahren zur sicheren Abspeicherung von Daten in nichtflüchtigen, überschreibbaren Speichern und Anlage zur Durchführung des Verfahrens
DE102005016801B4 (de) * 2005-04-12 2018-04-26 Robert Bosch Gmbh Verfahren und Rechnereinheit zur Fehlererkennung und Fehlerprotokollierung in einem Speicher
USD740125S1 (en) * 2014-03-26 2015-10-06 Gk Packaging, Inc. Bottle

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432232A (en) * 1977-08-17 1979-03-09 Toshiba Corp Check system for memory unit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/74 *
EXBK/77 *

Also Published As

Publication number Publication date
JPS54117641A (en) 1979-09-12
GB2016758A (en) 1979-09-26
DE2906789A1 (de) 1979-09-13
GB2016758B (en) 1982-10-06
DE2906789B2 (fr) 1980-05-08

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Legal Events

Date Code Title Description
ST Notification of lapse