FR2379198A1 - Horloge logique diphasee - Google Patents

Horloge logique diphasee

Info

Publication number
FR2379198A1
FR2379198A1 FR7702452A FR7702452A FR2379198A1 FR 2379198 A1 FR2379198 A1 FR 2379198A1 FR 7702452 A FR7702452 A FR 7702452A FR 7702452 A FR7702452 A FR 7702452A FR 2379198 A1 FR2379198 A1 FR 2379198A1
Authority
FR
France
Prior art keywords
source
cross coupled
coupled nand
logic clock
phase logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7702452A
Other languages
English (en)
Inventor
Jean-Louis Bourderiat
Michel Joumard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7702452A priority Critical patent/FR2379198A1/fr
Publication of FR2379198A1 publication Critical patent/FR2379198A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention se rapporte aux horloges logiques où deux signaux délivrés simultanément ne doivent jamais se trouver dans le même état logique Pour cela, à partir d'une horloge-mère H, le signal de commande o se partage en deux voies, et est appliqué à l'une des entrées de deux portes logiques << NON-ET >> 2, 3, sur voie A directement, et sur l'autre voie B après inversion dans un circuit inverseur 1. Selon l'invention, chaque porte réalise l'exclusion du fonctionnement de l'autre porte par raccordement de sa sortie à l'entrée restée libre de cette autre porte, selon un montage de type << basculeur >>. Les applications sont notamment du domaine des circuits pour microprocesseurs et des registres à décalage.
FR7702452A 1977-01-28 1977-01-28 Horloge logique diphasee Withdrawn FR2379198A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7702452A FR2379198A1 (fr) 1977-01-28 1977-01-28 Horloge logique diphasee

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7702452A FR2379198A1 (fr) 1977-01-28 1977-01-28 Horloge logique diphasee

Publications (1)

Publication Number Publication Date
FR2379198A1 true FR2379198A1 (fr) 1978-08-25

Family

ID=9186030

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7702452A Withdrawn FR2379198A1 (fr) 1977-01-28 1977-01-28 Horloge logique diphasee

Country Status (1)

Country Link
FR (1) FR2379198A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019348A1 (fr) * 1979-05-10 1980-11-26 The Wurlitzer Company Circuit de codage à trois états pour instrument de musique électronique
EP0053014A1 (fr) * 1980-11-20 1982-06-02 Fujitsu Limited Circuit de générateur de signaux d'horloge
FR2658370A1 (fr) * 1990-02-13 1991-08-16 Sgs Thomson Microelectronics Doubleur de frequence d'horloge.
EP0591022A1 (fr) * 1992-10-01 1994-04-06 STMicroelectronics S.A. Circuit élévateur de tension de type pompe de charge avec oscillateur bootstrappe

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019348A1 (fr) * 1979-05-10 1980-11-26 The Wurlitzer Company Circuit de codage à trois états pour instrument de musique électronique
EP0053014A1 (fr) * 1980-11-20 1982-06-02 Fujitsu Limited Circuit de générateur de signaux d'horloge
FR2658370A1 (fr) * 1990-02-13 1991-08-16 Sgs Thomson Microelectronics Doubleur de frequence d'horloge.
EP0442829A1 (fr) * 1990-02-13 1991-08-21 STMicroelectronics S.A. Doubleur de fréquence d'horloge
US5111066A (en) * 1990-02-13 1992-05-05 Sgs-Thompson Microelectronics S.A. Clock frequency doubler
EP0591022A1 (fr) * 1992-10-01 1994-04-06 STMicroelectronics S.A. Circuit élévateur de tension de type pompe de charge avec oscillateur bootstrappe
FR2696598A1 (fr) * 1992-10-01 1994-04-08 Sgs Thomson Microelectronics Circuit élévateur de tension de type pompe de charge avec oscillateur bootstrapé.
US5589793A (en) * 1992-10-01 1996-12-31 Sgs-Thomson Microelectronics S.A. Voltage booster circuit of the charge-pump type with bootstrapped oscillator
US5592115A (en) * 1992-10-01 1997-01-07 Sgs-Thomson Microelectronics S.A. Voltage booster circuit of the charge-pump type with a bootstrapped oscillator

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Legal Events

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