FR2330146A1 - Procede de gravure a alignement automatique d'une couche double de silicium polycristallin - Google Patents

Procede de gravure a alignement automatique d'une couche double de silicium polycristallin

Info

Publication number
FR2330146A1
FR2330146A1 FR7628293A FR7628293A FR2330146A1 FR 2330146 A1 FR2330146 A1 FR 2330146A1 FR 7628293 A FR7628293 A FR 7628293A FR 7628293 A FR7628293 A FR 7628293A FR 2330146 A1 FR2330146 A1 FR 2330146A1
Authority
FR
France
Prior art keywords
polycrystalline silicon
double layer
automatic alignment
engraving process
alignment engraving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7628293A
Other languages
English (en)
French (fr)
Other versions
FR2330146B1 (show.php
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2330146A1 publication Critical patent/FR2330146A1/fr
Application granted granted Critical
Publication of FR2330146B1 publication Critical patent/FR2330146B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H10P50/263—
FR7628293A 1975-10-29 1976-09-21 Procede de gravure a alignement automatique d'une couche double de silicium polycristallin Granted FR2330146A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62685975A 1975-10-29 1975-10-29

Publications (2)

Publication Number Publication Date
FR2330146A1 true FR2330146A1 (fr) 1977-05-27
FR2330146B1 FR2330146B1 (show.php) 1982-08-27

Family

ID=24512170

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7628293A Granted FR2330146A1 (fr) 1975-10-29 1976-09-21 Procede de gravure a alignement automatique d'une couche double de silicium polycristallin

Country Status (4)

Country Link
JP (1) JPS6020908B2 (show.php)
DE (1) DE2645014C3 (show.php)
FR (1) FR2330146A1 (show.php)
GB (1) GB1540450A (show.php)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0002997A3 (fr) * 1977-12-23 1979-09-19 International Business Machines Corporation Transistor à effet de champ à portes superposées et auto-alignées et procédé de fabrication
EP0013091A1 (en) * 1978-12-29 1980-07-09 Western Electric Company, Incorporated Fabrication of two-level polysilicon MOS devices
EP0023528A1 (en) * 1978-12-04 1981-02-11 Mostek Corporation Double diffused transistor structure and method of making same
FR2468185A1 (fr) * 1980-10-17 1981-04-30 Intel Corp Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite
EP0049392A3 (en) * 1980-10-06 1984-07-04 Siemens Aktiengesellschaft Method of making a two-transistor monolithic integrated memory cell using mos technology
FR2543738A1 (fr) * 1983-03-31 1984-10-05 Ates Componenti Elettron Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation
EP0085551A3 (en) * 1982-01-29 1986-06-04 Seeq Technology, Incorporated Method of fabricating an mos memory array having electrically-programmable and electrically-erasable storage devices incorporated therein

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089299B (it) 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS5419372A (en) * 1977-07-14 1979-02-14 Nec Corp Production of semiconductor memory
JPS54109785A (en) * 1978-02-16 1979-08-28 Nec Corp Semiconductor device
JPS5550667A (en) * 1978-10-09 1980-04-12 Fujitsu Ltd Method of fabricating double gate mos-type integrated circuit
JPS5787176A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Fabrication of semiconductor device
JPS57106171A (en) * 1980-12-24 1982-07-01 Fujitsu Ltd Manufacture of semiconductor device
JPS60187852A (ja) * 1984-03-07 1985-09-25 Shimadzu Corp Νｍｒ　ｃｔ装置における静磁場発生装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2116410A1 (show.php) * 1970-12-03 1972-07-13 Ncr Co
FR2148439A1 (show.php) * 1971-08-07 1973-03-23 Itt
FR2186737A1 (show.php) * 1972-05-30 1974-01-11 Westinghouse Electric Corp
FR2236247A1 (show.php) * 1973-07-05 1975-01-31 Tokyo Shibaura Electric Co

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2116410A1 (show.php) * 1970-12-03 1972-07-13 Ncr Co
FR2148439A1 (show.php) * 1971-08-07 1973-03-23 Itt
FR2186737A1 (show.php) * 1972-05-30 1974-01-11 Westinghouse Electric Corp
FR2236247A1 (show.php) * 1973-07-05 1975-01-31 Tokyo Shibaura Electric Co

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0002997A3 (fr) * 1977-12-23 1979-09-19 International Business Machines Corporation Transistor à effet de champ à portes superposées et auto-alignées et procédé de fabrication
EP0023528A1 (en) * 1978-12-04 1981-02-11 Mostek Corporation Double diffused transistor structure and method of making same
EP0013091A1 (en) * 1978-12-29 1980-07-09 Western Electric Company, Incorporated Fabrication of two-level polysilicon MOS devices
EP0049392A3 (en) * 1980-10-06 1984-07-04 Siemens Aktiengesellschaft Method of making a two-transistor monolithic integrated memory cell using mos technology
FR2468185A1 (fr) * 1980-10-17 1981-04-30 Intel Corp Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite
EP0085551A3 (en) * 1982-01-29 1986-06-04 Seeq Technology, Incorporated Method of fabricating an mos memory array having electrically-programmable and electrically-erasable storage devices incorporated therein
FR2543738A1 (fr) * 1983-03-31 1984-10-05 Ates Componenti Elettron Procede pour l'auto-alignement d'une double couche de silicium polycristallin, dans un dispositif a circuit integre, au moyen d'une operation d'oxydation

Also Published As

Publication number Publication date
DE2645014A1 (de) 1977-05-12
JPS5259585A (en) 1977-05-17
FR2330146B1 (show.php) 1982-08-27
DE2645014B2 (de) 1979-06-07
DE2645014C3 (de) 1980-02-28
GB1540450A (en) 1979-02-14
JPS6020908B2 (ja) 1985-05-24

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Legal Events

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