FR2235482A1 - Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props - Google Patents

Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props

Info

Publication number
FR2235482A1
FR2235482A1 FR7416726A FR7416726A FR2235482A1 FR 2235482 A1 FR2235482 A1 FR 2235482A1 FR 7416726 A FR7416726 A FR 7416726A FR 7416726 A FR7416726 A FR 7416726A FR 2235482 A1 FR2235482 A1 FR 2235482A1
Authority
FR
France
Prior art keywords
interface states
mios
structures
substrate
low temp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7416726A
Other languages
French (fr)
Other versions
FR2235482B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to FR7416726A priority Critical patent/FR2235482A1/en
Publication of FR2235482A1 publication Critical patent/FR2235482A1/en
Application granted granted Critical
Publication of FR2235482B1 publication Critical patent/FR2235482B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In fabrication of a semiconductor device, where an oxide layer (SiO2) is formed on a semiconductor (Si) substrate and an insulating layer (Si3N4 or Al2O3) on the oxide is pervious to gas diffusion only at high temps., interface states at the oxide-substrate interface are eliminated by (a) implanting H ions (through the insulating layer) at the interface region, capable of entering the substrate lattice and (b) annealing the substrate in an inert atmos. at time and temp. sufficient to eliminate the interface states, pref. 1/2-1 hr. at 450-600 degrees C.
FR7416726A 1974-05-07 1974-05-07 Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props Granted FR2235482A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7416726A FR2235482A1 (en) 1974-05-07 1974-05-07 Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7416726A FR2235482A1 (en) 1974-05-07 1974-05-07 Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props

Publications (2)

Publication Number Publication Date
FR2235482A1 true FR2235482A1 (en) 1975-01-24
FR2235482B1 FR2235482B1 (en) 1976-12-24

Family

ID=9138828

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7416726A Granted FR2235482A1 (en) 1974-05-07 1974-05-07 Eliminating interface states in MIOS structures - at low temp to avoid degradation of electrical props

Country Status (1)

Country Link
FR (1) FR2235482A1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1603354A (en) * 1967-08-02 1971-04-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1603354A (en) * 1967-08-02 1971-04-13

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
UE US "JOURNAL OF THE ELECTROCHEMICAL SOCIETY", VOLUME 116, NO. 11, NOVEMBRE 1969, "ANNEALING MECHANIST IN RADIATION DAMAGED MNOS STRUCTURES",J.J. TENTOR, ABSTRACT 233, PAGE 337C) *

Also Published As

Publication number Publication date
FR2235482B1 (en) 1976-12-24

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Legal Events

Date Code Title Description
ST Notification of lapse