FR2206014A5 - - Google Patents

Info

Publication number
FR2206014A5
FR2206014A5 FR7339357A FR7339357A FR2206014A5 FR 2206014 A5 FR2206014 A5 FR 2206014A5 FR 7339357 A FR7339357 A FR 7339357A FR 7339357 A FR7339357 A FR 7339357A FR 2206014 A5 FR2206014 A5 FR 2206014A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7339357A
Other languages
French (fr)
Inventor
F Nickel
J Swanson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Application granted granted Critical
Publication of FR2206014A5 publication Critical patent/FR2206014A5/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177Initialisation or configuration control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Storage Device Security (AREA)
  • Studio Circuits (AREA)
  • Hardware Redundancy (AREA)
FR7339357A 1972-11-06 1973-11-06 Expired FR2206014A5 (cg-RX-API-DMAC7.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00304172A US3832695A (en) 1972-11-06 1972-11-06 Partitioning circuit employing external interrupt signal

Publications (1)

Publication Number Publication Date
FR2206014A5 true FR2206014A5 (cg-RX-API-DMAC7.html) 1974-05-31

Family

ID=23175390

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7339357A Expired FR2206014A5 (cg-RX-API-DMAC7.html) 1972-11-06 1973-11-06

Country Status (10)

Country Link
US (1) US3832695A (cg-RX-API-DMAC7.html)
JP (1) JPS5710463B2 (cg-RX-API-DMAC7.html)
CA (1) CA1008182A (cg-RX-API-DMAC7.html)
CH (1) CH600432A5 (cg-RX-API-DMAC7.html)
DE (1) DE2354522C3 (cg-RX-API-DMAC7.html)
FR (1) FR2206014A5 (cg-RX-API-DMAC7.html)
GB (1) GB1451349A (cg-RX-API-DMAC7.html)
IT (1) IT999210B (cg-RX-API-DMAC7.html)
NL (1) NL7315159A (cg-RX-API-DMAC7.html)
SE (1) SE396148B (cg-RX-API-DMAC7.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124395U (cg-RX-API-DMAC7.html) * 1974-08-12 1976-02-23
DE2742035A1 (de) * 1977-09-19 1979-03-29 Siemens Ag Rechnersystem
US4484270A (en) * 1982-07-07 1984-11-20 Sperry Corporation Centralized hardware control of multisystem access to shared and non-shared subsystems
JPS5922120A (ja) * 1982-07-28 1984-02-04 Fanuc Ltd システム作成方式
EP0237841B1 (de) * 1986-03-21 1991-07-24 Siemens Aktiengesellschaft Verfahren zur Bearbeitung von Konfigurationsänderungen einer Datenverarbeitungsanlage und Vorrichtung zur Durchführung des Verfahrens
JPS63271587A (ja) * 1987-04-28 1988-11-09 Kyoritsu:Kk コ−ドシステム
JPS63273184A (ja) * 1987-04-30 1988-11-10 Kyoritsu:Kk コ−ドシステム
EP0348053B1 (en) * 1988-06-21 1995-08-16 Amdahl Corporation Controlling the initiation of logical systems in a data processing system with logical processor facility
GB2350212B (en) * 1999-02-09 2003-10-08 Adder Tech Ltd Data routing device and system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE568797A (cg-RX-API-DMAC7.html) * 1958-03-01
US3386082A (en) * 1965-06-02 1968-05-28 Ibm Configuration control in multiprocessors
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3680052A (en) * 1970-02-20 1972-07-25 Ibm Configuration control of data processing system units

Also Published As

Publication number Publication date
GB1451349A (en) 1976-09-29
IT999210B (it) 1976-02-20
DE2354522A1 (de) 1974-05-16
JPS4996654A (cg-RX-API-DMAC7.html) 1974-09-12
DE2354522C3 (de) 1978-12-07
US3832695A (en) 1974-08-27
NL7315159A (cg-RX-API-DMAC7.html) 1974-05-08
CH600432A5 (cg-RX-API-DMAC7.html) 1978-06-15
JPS5710463B2 (cg-RX-API-DMAC7.html) 1982-02-26
SE396148B (sv) 1977-09-05
CA1008182A (en) 1977-04-05
AU6204673A (en) 1975-05-01
DE2354522B2 (de) 1978-04-20

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Legal Events

Date Code Title Description
ST Notification of lapse