JPS5710463B2 - - Google Patents

Info

Publication number
JPS5710463B2
JPS5710463B2 JP12487173A JP12487173A JPS5710463B2 JP S5710463 B2 JPS5710463 B2 JP S5710463B2 JP 12487173 A JP12487173 A JP 12487173A JP 12487173 A JP12487173 A JP 12487173A JP S5710463 B2 JPS5710463 B2 JP S5710463B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12487173A
Other versions
JPS4996654A (ja
Inventor
F Nickel
J Swanson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of JPS4996654A publication Critical patent/JPS4996654A/ja
Publication of JPS5710463B2 publication Critical patent/JPS5710463B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177Initialisation or configuration control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Storage Device Security (AREA)
  • Hardware Redundancy (AREA)
  • Studio Circuits (AREA)
JP12487173A 1972-11-06 1973-11-06 Expired JPS5710463B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00304172A US3832695A (en) 1972-11-06 1972-11-06 Partitioning circuit employing external interrupt signal

Publications (2)

Publication Number Publication Date
JPS4996654A JPS4996654A (ja) 1974-09-12
JPS5710463B2 true JPS5710463B2 (ja) 1982-02-26

Family

ID=23175390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12487173A Expired JPS5710463B2 (ja) 1972-11-06 1973-11-06

Country Status (10)

Country Link
US (1) US3832695A (ja)
JP (1) JPS5710463B2 (ja)
CA (1) CA1008182A (ja)
CH (1) CH600432A5 (ja)
DE (1) DE2354522C3 (ja)
FR (1) FR2206014A5 (ja)
GB (1) GB1451349A (ja)
IT (1) IT999210B (ja)
NL (1) NL7315159A (ja)
SE (1) SE396148B (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124395U (ja) * 1974-08-12 1976-02-23
DE2742035A1 (de) * 1977-09-19 1979-03-29 Siemens Ag Rechnersystem
US4484270A (en) * 1982-07-07 1984-11-20 Sperry Corporation Centralized hardware control of multisystem access to shared and non-shared subsystems
JPS5922120A (ja) * 1982-07-28 1984-02-04 Fanuc Ltd システム作成方式
DE3771532D1 (de) * 1986-03-21 1991-08-29 Siemens Ag Verfahren zur bearbeitung von konfigurationsaenderungen einer datenverarbeitungsanlage und vorrichtung zur durchfuehrung des verfahrens.
JPS63271587A (ja) * 1987-04-28 1988-11-09 Kyoritsu:Kk コ−ドシステム
JPS63273184A (ja) * 1987-04-30 1988-11-10 Kyoritsu:Kk コ−ドシステム
DE68923829T2 (de) * 1988-06-21 1996-03-21 Amdahl Corp Startsteuerung von logischen Systemen in einem Datenverarbeitungssystem mit logischer Prozessormöglichkeit.
GB2350212B (en) * 1999-02-09 2003-10-08 Adder Tech Ltd Data routing device and system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL239887A (ja) * 1958-03-01
US3386082A (en) * 1965-06-02 1968-05-28 Ibm Configuration control in multiprocessors
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3680052A (en) * 1970-02-20 1972-07-25 Ibm Configuration control of data processing system units

Also Published As

Publication number Publication date
DE2354522A1 (de) 1974-05-16
FR2206014A5 (ja) 1974-05-31
CA1008182A (en) 1977-04-05
GB1451349A (en) 1976-09-29
DE2354522B2 (de) 1978-04-20
NL7315159A (ja) 1974-05-08
SE396148B (sv) 1977-09-05
DE2354522C3 (de) 1978-12-07
AU6204673A (en) 1975-05-01
CH600432A5 (ja) 1978-06-15
IT999210B (it) 1976-02-20
JPS4996654A (ja) 1974-09-12
US3832695A (en) 1974-08-27

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