FR2133692A1 - - Google Patents
Info
- Publication number
- FR2133692A1 FR2133692A1 FR7213006A FR7213006A FR2133692A1 FR 2133692 A1 FR2133692 A1 FR 2133692A1 FR 7213006 A FR7213006 A FR 7213006A FR 7213006 A FR7213006 A FR 7213006A FR 2133692 A1 FR2133692 A1 FR 2133692A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/67—Complementary BJTs
- H10D84/673—Vertical complementary BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/87—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of PN-junction gate FETs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7105000A NL7105000A (enrdf_load_stackoverflow) | 1971-04-14 | 1971-04-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2133692A1 true FR2133692A1 (enrdf_load_stackoverflow) | 1972-12-01 |
FR2133692B1 FR2133692B1 (enrdf_load_stackoverflow) | 1977-08-19 |
Family
ID=19812915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7213006A Expired FR2133692B1 (enrdf_load_stackoverflow) | 1971-04-14 | 1972-04-13 |
Country Status (11)
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL161301C (nl) * | 1972-12-29 | 1980-01-15 | Philips Nv | Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan. |
JPS5534619U (enrdf_load_stackoverflow) * | 1978-08-25 | 1980-03-06 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2030578A6 (fr) * | 1967-12-05 | 1970-11-13 | Sony Corp | Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus |
-
1971
- 1971-04-14 NL NL7105000A patent/NL7105000A/xx not_active Application Discontinuation
-
1972
- 1972-04-07 DE DE2216642A patent/DE2216642C3/de not_active Expired
- 1972-04-10 AU AU40936/72A patent/AU470407B2/en not_active Expired
- 1972-04-11 CH CH531272A patent/CH539952A/de not_active IP Right Cessation
- 1972-04-11 GB GB1660972A patent/GB1387021A/en not_active Expired
- 1972-04-11 IT IT23017/72A patent/IT951314B/it active
- 1972-04-11 SE SE7204673A patent/SE383582B/xx unknown
- 1972-04-12 ES ES401687A patent/ES401687A1/es not_active Expired
- 1972-04-12 BE BE782012A patent/BE782012A/xx unknown
- 1972-04-13 FR FR7213006A patent/FR2133692B1/fr not_active Expired
- 1972-04-14 BR BR2251/72A patent/BR7202251D0/pt unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2030578A6 (fr) * | 1967-12-05 | 1970-11-13 | Sony Corp | Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus |
Non-Patent Citations (4)
Title |
---|
(REVUE US:"ELECTRONICS",VOL.44,NO5,1 MARS 1971"ISOLATION METHOD SHRINKS BIPOLAR CELLS FOR FAST, DENSEMEMORIES" * |
D.PELTZER ET B.HERNDON,PAGES 53-55.) * |
DENSEMEMORIES" * |
REVUE US:"ELECTRONICS",VOL.44,NO5,1 MARS 1971"ISOLATION METHOD SHRINKS BIPOLAR CELLS FOR FAST, * |
Also Published As
Publication number | Publication date |
---|---|
BR7202251D0 (pt) | 1973-06-07 |
AU470407B2 (en) | 1973-10-18 |
FR2133692B1 (enrdf_load_stackoverflow) | 1977-08-19 |
CH539952A (de) | 1973-07-31 |
SE383582B (sv) | 1976-03-15 |
DE2216642C3 (de) | 1979-12-13 |
NL7105000A (enrdf_load_stackoverflow) | 1972-10-17 |
DE2216642A1 (de) | 1972-10-19 |
ES401687A1 (es) | 1975-03-16 |
GB1387021A (en) | 1975-03-12 |
BE782012A (fr) | 1972-10-13 |
IT951314B (it) | 1973-06-30 |
AU4093672A (en) | 1973-10-18 |
DE2216642B2 (de) | 1979-04-12 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |