FR2074233A5 - - Google Patents

Info

Publication number
FR2074233A5
FR2074233A5 FR7046476A FR7046476A FR2074233A5 FR 2074233 A5 FR2074233 A5 FR 2074233A5 FR 7046476 A FR7046476 A FR 7046476A FR 7046476 A FR7046476 A FR 7046476A FR 2074233 A5 FR2074233 A5 FR 2074233A5
Authority
FR
France
Prior art keywords
type
conductivity type
gold
alloy
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7046476A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of FR2074233A5 publication Critical patent/FR2074233A5/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53247Noble-metal alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13021Disposition the bump connector being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
FR7046476A 1969-12-26 1970-12-23 Expired FR2074233A5 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP441769 1969-12-26
JP10441769 1969-12-26

Publications (1)

Publication Number Publication Date
FR2074233A5 true FR2074233A5 (fr) 1971-10-01

Family

ID=26338176

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7046476A Expired FR2074233A5 (fr) 1969-12-26 1970-12-23

Country Status (5)

Country Link
US (1) US3686698A (fr)
DE (1) DE2062897A1 (fr)
FR (1) FR2074233A5 (fr)
GB (1) GB1337283A (fr)
NL (1) NL7018311A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2606551A1 (fr) * 1986-11-07 1988-05-13 Arnaud D Avitaya Francois Procede de formation de contacts ohmiques sur du silicium

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789498A (fr) * 1971-09-29 1973-01-15 Siemens Ag Contact metal-semiconducteur de faible superficie
DE2634263A1 (de) * 1976-07-30 1978-02-02 Licentia Gmbh Mehrschichtiger metallanschlusskontakt
DE2603745C3 (de) * 1976-01-31 1981-07-23 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Mehrschichtiger Metallanschlußkontakt und Verfahren zu seiner Herstellung
DE3025859A1 (de) * 1980-07-08 1982-01-28 Siemens AG, 1000 Berlin und 8000 München Verfahren zum aufbringen einer metallschicht auf einen halbleiterkoerper
JPS59213145A (ja) * 1983-05-18 1984-12-03 Toshiba Corp 半導体装置及びその製造方法
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device
DE68927931T2 (de) * 1989-07-26 1997-09-18 Ibm Verfahren zur Herstellung einer Packungsstruktur für einen integrierten Schaltungschip
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5349239A (en) * 1991-07-04 1994-09-20 Sharp Kabushiki Kaisha Vertical type construction transistor
US5411400A (en) * 1992-09-28 1995-05-02 Motorola, Inc. Interconnect system for a semiconductor chip and a substrate
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
US6100194A (en) * 1998-06-22 2000-08-08 Stmicroelectronics, Inc. Silver metallization by damascene method
JP2002124654A (ja) * 2000-10-13 2002-04-26 Mitsubishi Electric Corp 固体撮像装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3172829A (en) * 1961-01-24 1965-03-09 Of an alloy to a support
NL135880C (fr) * 1961-07-12 1900-01-01
BE620118A (fr) * 1961-07-14
NL297607A (fr) * 1962-09-07
GB1095047A (en) * 1964-09-09 1967-12-13 Westinghouse Brake & Signal Semi-conductor devices and the manufacture thereof
US3408271A (en) * 1965-03-01 1968-10-29 Hughes Aircraft Co Electrolytic plating of metal bump contacts to semiconductor devices upon nonconductive substrates
US3510734A (en) * 1967-10-18 1970-05-05 Hughes Aircraft Co Impatt diode
US3496428A (en) * 1968-04-11 1970-02-17 Itt Diffusion barrier for semiconductor contacts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2606551A1 (fr) * 1986-11-07 1988-05-13 Arnaud D Avitaya Francois Procede de formation de contacts ohmiques sur du silicium

Also Published As

Publication number Publication date
DE2062897A1 (de) 1971-07-15
GB1337283A (en) 1973-11-14
NL7018311A (fr) 1971-06-29
US3686698A (en) 1972-08-29

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Legal Events

Date Code Title Description
ST Notification of lapse