FI96068B - Device for operation of a redundant multi-processor system for controlling an electronic switchgear - Google Patents

Device for operation of a redundant multi-processor system for controlling an electronic switchgear

Info

Publication number
FI96068B
FI96068B FI894266A FI894266A FI96068B FI 96068 B FI96068 B FI 96068B FI 894266 A FI894266 A FI 894266A FI 894266 A FI894266 A FI 894266A FI 96068 B FI96068 B FI 96068B
Authority
FI
Finland
Prior art keywords
processor
operation control
brr
operating
processors
Prior art date
Application number
FI894266A
Other languages
Finnish (fi)
Swedish (sv)
Other versions
FI96068C (en
FI894266A (en
FI894266A0 (en
Inventor
Guenther Reichelt
Rudolf Guenther
Norbert Geduhn
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI894266A0 publication Critical patent/FI894266A0/en
Publication of FI894266A publication Critical patent/FI894266A/en
Publication of FI96068B publication Critical patent/FI96068B/en
Application granted granted Critical
Publication of FI96068C publication Critical patent/FI96068C/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023Failover techniques
    • G06F11/2028Failover techniques eliminating a faulty processor or activating a spare
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B61RAILWAYS
    • B61LGUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L1/00Devices along the route controlled by interaction with the vehicle or train
    • B61L1/20Safety arrangements for preventing or indicating malfunction of the device, e.g. by leakage current, by lightning
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B61RAILWAYS
    • B61LGUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L19/00Arrangements for interlocking between points and signals by means of a single interlocking device, e.g. central control
    • B61L19/06Interlocking devices having electrical operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023Failover techniques
    • G06F11/2025Failover techniques using centralised failover control functionality
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Hardware Redundancy (AREA)
  • Electric Propulsion And Braking For Vehicles (AREA)
  • Safety Devices In Control Systems (AREA)
  • Multi Processors (AREA)

Abstract

Device for operating a redundant multiprocessor system for the control of an electronic signal mechanism. A coordination processor (ER) assigns to each operation control area processor (BR1, BR2) an operating address ("07", "08"), transmits this by means of a module address ("87", "88") to the processors and provides the processors with the data required for process control. The operation control processors (BR1, BR2) communicate with one another and with the coordination processor using the operating addresses allocated to them. If the coordination processor (ER) detects the failure of an operation control processor (BR1), and if an operational standby processor (BRR) is available, then the coordination processor assigns the operating address ("07") of the failed processor (BR1) to this processor (BRR) by addressing it via its module address ("89"), provides it with the relevant data for process control and includes it as the new operation control processor in the processor network. The remaining operation control processors (BR2) communicate with the previous standby processor (BRR) using the operating address ("07") allocated to the previous operation control processor (BR1) and now to the previous standby processor (BRR) without being informed that anything has changed in the hardware of the processor network as a result of the failure of a processor (BR1) and the activation of a standby processor (BRR). <IMAGE>
FI894266A 1988-09-12 1989-09-11 Device for operation of a redundant multi-processor system for controlling an electronic switchgear FI96068C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP88114889A EP0358785B1 (en) 1988-09-12 1988-09-12 Device for operating a redundant multiprocessor system for the control of an electronic signal mechanism in the train signal technique
EP88114889 1988-09-12

Publications (4)

Publication Number Publication Date
FI894266A0 FI894266A0 (en) 1989-09-11
FI894266A FI894266A (en) 1990-03-13
FI96068B true FI96068B (en) 1996-01-15
FI96068C FI96068C (en) 1996-04-25

Family

ID=8199298

Family Applications (1)

Application Number Title Priority Date Filing Date
FI894266A FI96068C (en) 1988-09-12 1989-09-11 Device for operation of a redundant multi-processor system for controlling an electronic switchgear

Country Status (5)

Country Link
EP (1) EP0358785B1 (en)
AT (1) ATE97753T1 (en)
DE (1) DE3885896D1 (en)
FI (1) FI96068C (en)
ZA (1) ZA896906B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2682201B1 (en) * 1991-10-04 1994-01-14 Aerospatiale Ste Nationale Indle METHOD FOR THE TEMPORAL DISCRIMINATION OF FAULTS IN A HIERARCHIZED DATA PROCESSING SYSTEM, AND HIERARCHED DATA PROCESSING SYSTEM SUITABLE FOR ITS IMPLEMENTATION.
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
DE69916990T2 (en) * 1999-01-11 2005-04-21 Koken Co Fault-tolerant computer system
DE10006760B4 (en) * 2000-02-15 2005-02-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Production of a Protein Biosensor with a Defined Binding Matrix
US8572431B2 (en) * 2005-02-23 2013-10-29 Barclays Capital Inc. Disaster recovery framework
DE102005046456B4 (en) * 2005-09-20 2007-06-06 Siemens Ag Method for determining the location and / or a movement quantity of moving objects, in particular of moving track-bound vehicles
DE102016225424A1 (en) * 2016-12-19 2018-06-21 Siemens Aktiengesellschaft Railway system and method for its operation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3323269A1 (en) * 1983-06-28 1985-01-10 Siemens AG, 1000 Berlin und 8000 München DEVICE FOR THE OPERATION OF A COMPUTER-CONTROLLED ACTUATOR
US4718002A (en) * 1985-06-05 1988-01-05 Tandem Computers Incorporated Method for multiprocessor communications
US4710926A (en) * 1985-12-27 1987-12-01 American Telephone And Telegraph Company, At&T Bell Laboratories Fault recovery in a distributed processing system
FR2606184B1 (en) * 1986-10-31 1991-11-29 Thomson Csf RECONFIGURABLE CALCULATION DEVICE

Also Published As

Publication number Publication date
DE3885896D1 (en) 1994-01-05
EP0358785A1 (en) 1990-03-21
ZA896906B (en) 1990-06-27
EP0358785B1 (en) 1993-11-24
FI96068C (en) 1996-04-25
FI894266A (en) 1990-03-13
ATE97753T1 (en) 1993-12-15
FI894266A0 (en) 1989-09-11

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Legal Events

Date Code Title Description
BB Publication of examined application
MM Patent lapsed

Owner name: SIEMENS AKTIENGESELLSCHAFT