KR940000976A - Booting Method and Device of Multiprocessor System - Google Patents

Booting Method and Device of Multiprocessor System Download PDF

Info

Publication number
KR940000976A
KR940000976A KR1019920010145A KR920010145A KR940000976A KR 940000976 A KR940000976 A KR 940000976A KR 1019920010145 A KR1019920010145 A KR 1019920010145A KR 920010145 A KR920010145 A KR 920010145A KR 940000976 A KR940000976 A KR 940000976A
Authority
KR
South Korea
Prior art keywords
booting
processors
booting program
program
management processor
Prior art date
Application number
KR1019920010145A
Other languages
Korean (ko)
Other versions
KR970002882B1 (en
Inventor
이현철
Original Assignee
정장호
금성정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정장호, 금성정보통신 주식회사 filed Critical 정장호
Priority to KR1019920010145A priority Critical patent/KR970002882B1/en
Publication of KR940000976A publication Critical patent/KR940000976A/en
Application granted granted Critical
Publication of KR970002882B1 publication Critical patent/KR970002882B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4405Initialisation of multiprocessor systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Stored Programmes (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 다중 프로세서 시스템에 관한 것으로, 복수의 슬레이브 프로세서를 동작시키기 위한 부팅 프로그램을 효율성 있게 로딩 시킬 수 있도록 한 다중 프로세서 시스템의 부팅 방법 및 장치에 관한 것이다.The present invention relates to a multiprocessor system, and more particularly, to a booting method and apparatus for enabling a multiprocessor system to load a boot program for operating a plurality of slave processors.

본 발명은 복수의 부팅용 ROM을 구비하지 않아도 되므로 다중 프로세서 시스템의 회로부피를 감소시키고 부팅 프로그램을 자유롭게 변경시킬 수 있으므로 부팅 프로그램의 유지관리를 용이하게 할 수 있다.Since the present invention does not have to include a plurality of boot ROMs, the circuit volume of the multiprocessor system can be reduced and the boot program can be freely changed, thereby facilitating maintenance of the boot program.

Description

다중 프로세서 시스템의 부팅방법 및 장치Booting Method and Device of Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 다중프로세서 시스템의 부팅장치 블럭도.2 is a block diagram of a boot device of a multiprocessor system according to the present invention.

Claims (3)

다중 프로세서 시스템의 부팅방법에 있어서, 복수 프로세서중의 일부 또는 전부로 부터 부팅 프로그램 로딩 요구가 있을때 별도의 프로세서에 의해 부팅 프로그램 로딩 요구한 상기 복수 프로세서의 RAM측으로 부팅 프로그램을 보내고, 부팅 프로그램 로딩요구한 상기 복수의 프로세서는 상기 RAM에 저장된 부팅 프로그램을 이용해 초기동작을 수행하는 것을 특징으로 하는 다중 프로세서 시스템의 부팅방법.In the booting method of a multiprocessor system, when a boot program loading request is received from some or all of the multiple processors, a boot program is sent to the RAM side of the multiprocessor which has requested boot program loading by a separate processor, and the boot program loading request is requested. And the plurality of processors perform an initial operation using a booting program stored in the RAM. 다중 프로세서 시스템의 부팅장치에 있어서, 복수 프로세서중의 일부 또는 전부로 부터 부팅 프로그램 로딩 요구가 있을때 부팅 프로그램 요구한 상기 복수 프로세서의 RAM 측으로 부팅 프로그램을 공급하는 부팅프로그램 관리용 프로세서와, 부팅 프로그램로딩 요구한 상기 복수 프로세서와 상기 부팅 프로그램 관리용 프로세서간의 데이타 흐름을 제어하는 복수의 버퍼와, 상기 부팅 프로그램 관리용 프로세서의 제어에 따라 상기 복수의 버퍼 측으로 제어 신호를 공급하는 버스제어부와, 상기 부팅 프로그램 관리용 프로세서의 제어에 따라 부팅 프로그램 로딩 요구한 상기 복수 프로세서측으로 리세트 신호를 공급하는 리세트 제어부를 구비한 것을 특징으로 하는 다중 프로세서 시스템의 부팅장치.A booting apparatus for a multiprocessor system, comprising: a booting program management processor for supplying a booting program to a RAM side of the multiprocessor requesting a booting program when a booting program loading request is received from some or all of the plurality of processors, and a booting program loading request A plurality of buffers for controlling data flow between the plurality of processors and the booting program management processor, a bus control unit supplying control signals to the plurality of buffers under control of the booting program management processor, and the booting program management And a reset control unit for supplying a reset signal to the plurality of processors requesting a boot program loading according to the control of the processor. 제2항에 있어서, 상기 리세트 제어부는 상기 부팅 프로그램 관리용 프로세서가 부팅 프로그램 로딩 요구한 상기 복수 프로세서의 RAM측으로 부팅 프로그램 공급을 완료했을때 상기 부팅 프로그램 관리용 프로세서의 제어에 따라 부팅 프로그램 로딩 요구한 상기 복수 프로세서 측으로 리세트 신호를 공급하여 부팅 프로그램 로딩 요구한 상기 복수 프로세서를 동작시키는 것을 특징으로 하는 다중 프로세서 시스템의 부팅장치.The booting program load request according to claim 2, wherein the reset control unit requests a booting program load under the control of the booting program management processor when the booting program management processor completes supplying a booting program to the RAM side of the plurality of processors requested by the booting program management processor. And providing a reset signal to one of the plurality of processors to operate the plurality of processors that have requested a boot program loading. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920010145A 1992-06-11 1992-06-11 Method and apparatus for bootstrap program loading in multiprocessor system KR970002882B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920010145A KR970002882B1 (en) 1992-06-11 1992-06-11 Method and apparatus for bootstrap program loading in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920010145A KR970002882B1 (en) 1992-06-11 1992-06-11 Method and apparatus for bootstrap program loading in multiprocessor system

Publications (2)

Publication Number Publication Date
KR940000976A true KR940000976A (en) 1994-01-10
KR970002882B1 KR970002882B1 (en) 1997-03-12

Family

ID=19334542

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920010145A KR970002882B1 (en) 1992-06-11 1992-06-11 Method and apparatus for bootstrap program loading in multiprocessor system

Country Status (1)

Country Link
KR (1) KR970002882B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101255382B1 (en) * 2005-01-22 2013-04-17 텔레폰악티에볼라겟엘엠에릭슨(펍) Operating-system-friendly bootloader

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101118111B1 (en) * 2005-07-08 2012-03-12 엘지전자 주식회사 Mobile communication terminal and booting method thereof
KR101275752B1 (en) * 2005-12-06 2013-06-17 삼성전자주식회사 Memory system and booting method thereof
JP2007213292A (en) 2006-02-09 2007-08-23 Nec Electronics Corp Method for starting multiprocessor system and slave system
KR20120035716A (en) * 2010-10-06 2012-04-16 주식회사 유니듀 Apparatus and method of booting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101255382B1 (en) * 2005-01-22 2013-04-17 텔레폰악티에볼라겟엘엠에릭슨(펍) Operating-system-friendly bootloader

Also Published As

Publication number Publication date
KR970002882B1 (en) 1997-03-12

Similar Documents

Publication Publication Date Title
KR850000718A (en) Multi Processor System
DE3688363D1 (en) INTERRUPTION PROCESSING IN A MULTIPROCESSOR COMPUTER SYSTEM.
ATE39581T1 (en) MICROCOMPUTER DATA PROCESSING SYSTEMS ALLOWING BUS CONTROL BY PERIPHERAL PROCESSORS.
KR950033878A (en) Bus system
GB1373828A (en) Data processing systems
KR940000976A (en) Booting Method and Device of Multiprocessor System
KR930002958A (en) Memory sharing device for interprocessor communication
KR870011540A (en) System Management System for Multiprocessor Systems
KR930010742A (en) Memory access device
KR940018763A (en) A method and apparatus for improving data transfer efficiency of multiple processors from memory in a data processing device.
KR920008602A (en) Computer system with multiple input / output devices sharing address space and communication management method between input / output device and processor
KR910008592A (en) Delay logic to prevent release of bus ownership of the CPU
KR960015249A (en) Apparatus and method for controlling automatic frame transmission during I / O channel and peripheral device control period in data processing system
KR970016886A (en) Information processing system with efficient power-on initialization
KR960029993A (en) Interrupt control device in the computer field
JPS5674738A (en) Transfer system of display data
JPS56143072A (en) Hung up release and processing system in multiprocessor processing system
KR970012172A (en) BUS CONTROLLER DEVICE FOR MULTI-Microprocessors
KR970016992A (en) Interrupt Controller of Shared I / O Control Board in Multiprocessor System
KR930004870A (en) Real time processing system with VSB interfacing graphic board
KR950033845A (en) Data consistency maintainer between on-chip cache and external cache
KR970012196A (en) System redundancy implementing device including shared memory
KR910012965A (en) Interrupt Methods in Multiprocessor Systems
KR890017620A (en) Multibus microcomputer system
KR890013567A (en) Direct Memory Access Control

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110214

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee