ZA896906B - System for operating a redundant multicomputer system for controlling an electronic signal box - Google Patents

System for operating a redundant multicomputer system for controlling an electronic signal box

Info

Publication number
ZA896906B
ZA896906B ZA896906A ZA896906A ZA896906B ZA 896906 B ZA896906 B ZA 896906B ZA 896906 A ZA896906 A ZA 896906A ZA 896906 A ZA896906 A ZA 896906A ZA 896906 B ZA896906 B ZA 896906B
Authority
ZA
South Africa
Prior art keywords
processor
operating
operation control
brr
processors
Prior art date
Application number
ZA896906A
Inventor
Guenther Reichelt
Reichelt Guenther
Rudolf Guenther
Guenther Rudolf
Norbert Geduhn
Geduhn Norbert
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of ZA896906B publication Critical patent/ZA896906B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L1/00—Devices along the route controlled by interaction with the vehicle or train
    • B61L1/20—Safety arrangements for preventing or indicating malfunction of the device, e.g. by leakage current, by lightning
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L19/00—Arrangements for interlocking between points and signals by means of a single interlocking device, e.g. central control
    • B61L19/06—Interlocking devices having electrical operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Hardware Redundancy (AREA)
  • Electric Propulsion And Braking For Vehicles (AREA)
  • Safety Devices In Control Systems (AREA)
  • Multi Processors (AREA)

Abstract

Device for operating a redundant multiprocessor system for the control of an electronic signal mechanism. A coordination processor (ER) assigns to each operation control area processor (BR1, BR2) an operating address ("07", "08"), transmits this by means of a module address ("87", "88") to the processors and provides the processors with the data required for process control. The operation control processors (BR1, BR2) communicate with one another and with the coordination processor using the operating addresses allocated to them. If the coordination processor (ER) detects the failure of an operation control processor (BR1), and if an operational standby processor (BRR) is available, then the coordination processor assigns the operating address ("07") of the failed processor (BR1) to this processor (BRR) by addressing it via its module address ("89"), provides it with the relevant data for process control and includes it as the new operation control processor in the processor network. The remaining operation control processors (BR2) communicate with the previous standby processor (BRR) using the operating address ("07") allocated to the previous operation control processor (BR1) and now to the previous standby processor (BRR) without being informed that anything has changed in the hardware of the processor network as a result of the failure of a processor (BR1) and the activation of a standby processor (BRR). <IMAGE>
ZA896906A 1988-09-12 1989-09-11 System for operating a redundant multicomputer system for controlling an electronic signal box ZA896906B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP88114889A EP0358785B1 (en) 1988-09-12 1988-09-12 Device for operating a redundant multiprocessor system for the control of an electronic signal mechanism in the train signal technique

Publications (1)

Publication Number Publication Date
ZA896906B true ZA896906B (en) 1990-06-27

Family

ID=8199298

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA896906A ZA896906B (en) 1988-09-12 1989-09-11 System for operating a redundant multicomputer system for controlling an electronic signal box

Country Status (5)

Country Link
EP (1) EP0358785B1 (en)
AT (1) ATE97753T1 (en)
DE (1) DE3885896D1 (en)
FI (1) FI96068C (en)
ZA (1) ZA896906B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2682201B1 (en) * 1991-10-04 1994-01-14 Aerospatiale Ste Nationale Indle METHOD FOR THE TEMPORAL DISCRIMINATION OF FAULTS IN A HIERARCHIZED DATA PROCESSING SYSTEM, AND HIERARCHED DATA PROCESSING SYSTEM SUITABLE FOR ITS IMPLEMENTATION.
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
EP1020797B1 (en) * 1999-01-11 2004-05-06 Koken Co., Ltd. Fault tolerant computer system
DE10006760B4 (en) * 2000-02-15 2005-02-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Production of a Protein Biosensor with a Defined Binding Matrix
US8572431B2 (en) * 2005-02-23 2013-10-29 Barclays Capital Inc. Disaster recovery framework
DE102005046456B4 (en) * 2005-09-20 2007-06-06 Siemens Ag Method for determining the location and / or a movement quantity of moving objects, in particular of moving track-bound vehicles
DE102016225424A1 (en) * 2016-12-19 2018-06-21 Siemens Aktiengesellschaft Railway system and method for its operation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3323269A1 (en) * 1983-06-28 1985-01-10 Siemens AG, 1000 Berlin und 8000 München DEVICE FOR THE OPERATION OF A COMPUTER-CONTROLLED ACTUATOR
US4718002A (en) * 1985-06-05 1988-01-05 Tandem Computers Incorporated Method for multiprocessor communications
US4710926A (en) * 1985-12-27 1987-12-01 American Telephone And Telegraph Company, At&T Bell Laboratories Fault recovery in a distributed processing system
FR2606184B1 (en) * 1986-10-31 1991-11-29 Thomson Csf RECONFIGURABLE CALCULATION DEVICE

Also Published As

Publication number Publication date
FI894266A0 (en) 1989-09-11
FI96068C (en) 1996-04-25
DE3885896D1 (en) 1994-01-05
EP0358785A1 (en) 1990-03-21
ATE97753T1 (en) 1993-12-15
FI894266A (en) 1990-03-13
EP0358785B1 (en) 1993-11-24
FI96068B (en) 1996-01-15

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