FI953953A0 - Signaaliprosessointipiiri ja menetelmä, jolla viivästetään binääristä, jaksollista tulosignaalia - Google Patents

Signaaliprosessointipiiri ja menetelmä, jolla viivästetään binääristä, jaksollista tulosignaalia

Info

Publication number
FI953953A0
FI953953A0 FI953953A FI953953A FI953953A0 FI 953953 A0 FI953953 A0 FI 953953A0 FI 953953 A FI953953 A FI 953953A FI 953953 A FI953953 A FI 953953A FI 953953 A0 FI953953 A0 FI 953953A0
Authority
FI
Finland
Prior art keywords
delaying
binary
processing circuit
periodic input
signal processing
Prior art date
Application number
FI953953A
Other languages
English (en)
Swedish (sv)
Other versions
FI953953A (fi
Inventor
Nils Per Aoke Liedberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of FI953953A0 publication Critical patent/FI953953A0/fi
Publication of FI953953A publication Critical patent/FI953953A/fi

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
FI953953A 1993-02-24 1995-08-23 Signaaliprosessointipiiri ja menetelmä, jolla viivästetään binääristä, jaksollista tulosignaalia FI953953A (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9300624A SE500929C2 (sv) 1993-02-24 1993-02-24 Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal
PCT/SE1994/000088 WO1994019868A1 (en) 1993-02-24 1994-02-04 A signal processing circuit and a method of delaying a binary periodic input signal

Publications (2)

Publication Number Publication Date
FI953953A0 true FI953953A0 (fi) 1995-08-23
FI953953A FI953953A (fi) 1995-08-23

Family

ID=20389021

Family Applications (1)

Application Number Title Priority Date Filing Date
FI953953A FI953953A (fi) 1993-02-24 1995-08-23 Signaaliprosessointipiiri ja menetelmä, jolla viivästetään binääristä, jaksollista tulosignaalia

Country Status (13)

Country Link
US (1) US5471165A (fi)
EP (1) EP0686319A1 (fi)
JP (1) JPH08506949A (fi)
KR (1) KR960701512A (fi)
CN (1) CN1118205A (fi)
AU (1) AU676022B2 (fi)
BR (1) BR9406373A (fi)
CA (1) CA2154252A1 (fi)
FI (1) FI953953A (fi)
MX (1) MXPA94001092A (fi)
NO (1) NO953307L (fi)
SE (1) SE500929C2 (fi)
WO (1) WO1994019868A1 (fi)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2710800B1 (fr) * 1993-09-27 1995-12-15 Sgs Thomson Microelectronics Ligne à retard numérique.
JP3639000B2 (ja) * 1995-06-13 2005-04-13 富士通株式会社 位相合わせ装置及び遅延制御回路
JPH10117142A (ja) * 1996-10-11 1998-05-06 Fujitsu Ltd 位相同期ループ回路および半導体集積回路
JPH1131964A (ja) * 1997-07-11 1999-02-02 Hitachi Ltd 論理回路
US6128680A (en) * 1997-12-18 2000-10-03 Alcatel Usa Sourcing, L.P. Apparatus and method of sharing a state machine for input and output signal processing
US6144034A (en) * 1998-07-22 2000-11-07 Adac Laboratories Delay calibration for gamma camera timing circuit
DE69801827T2 (de) 1998-11-14 2002-03-28 Agilent Technologies, Inc. (N.D.Ges.D.Staates Delaware) Taktgenerator
DE19933115A1 (de) 1999-07-19 2001-01-25 Mannesmann Vdo Ag Verfahren zur Modulation eines Grundtaktes für digitale Schaltungen und Taktmodulator zur Ausführung des Verfahrens
US7805628B2 (en) * 2001-04-02 2010-09-28 Credence Systems Corporation High resolution clock signal generator
US20040232954A1 (en) * 2001-07-06 2004-11-25 Van Zeijl Paulus Thomas Signal generator device, method for generating a signal and devices including such a signal generator device
US7020792B2 (en) * 2002-04-30 2006-03-28 Intel Corporation Method and apparatus for time domain equalization
WO2003098414A1 (en) * 2002-05-16 2003-11-27 Infineon Technologies Ag Apparatus for adjusting the phase of a digital signal
KR100493046B1 (ko) * 2003-02-04 2005-06-07 삼성전자주식회사 클럭의 듀티 사이클을 조정할 수 있는 주파수 체배기 및체배방법
US7109768B2 (en) * 2004-06-29 2006-09-19 Intel Corporation Closed-loop control of driver slew rate
US8842766B2 (en) * 2010-03-31 2014-09-23 Texas Instruments Incorporated Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks
CN101895274B (zh) * 2010-07-21 2013-04-10 珠海天威技术开发有限公司 数字滤波电路及其滤波方法、耗材芯片
CN104079274A (zh) * 2013-03-26 2014-10-01 佛山市顺德区顺达电脑厂有限公司 分析用信号延时装置及其方法
CN108390666A (zh) * 2018-04-26 2018-08-10 佛山科学技术学院 一种延时电路

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
US4494021A (en) * 1982-08-30 1985-01-15 Xerox Corporation Self-calibrated clock and timing signal generator for MOS/VLSI circuitry
JPS5972814A (ja) * 1982-10-20 1984-04-24 Sanyo Electric Co Ltd 遅延回路
JPS61163715A (ja) * 1985-01-14 1986-07-24 Nec Corp 遅延線を用いた多相クロツク発生回路
JPS6270922A (ja) * 1985-09-04 1987-04-01 Fujitsu Ltd クロツク位相調整方式
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
CA1254957A (en) * 1986-11-07 1989-05-30 Mitel Corporation Frequency doubler
US5173617A (en) * 1988-06-27 1992-12-22 Motorola, Inc. Digital phase lock clock generator without local oscillator
EP0476585B1 (en) * 1990-09-18 1998-08-26 Fujitsu Limited Electronic device using a reference delay generator
US5159205A (en) * 1990-10-24 1992-10-27 Burr-Brown Corporation Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line
JPH07142997A (ja) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> ディレイ・ライン較正回路
US5223755A (en) * 1990-12-26 1993-06-29 Xerox Corporation Extended frequency range variable delay locked loop for clock synchronization
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5295164A (en) * 1991-12-23 1994-03-15 Apple Computer, Inc. Apparatus for providing a system clock locked to an external clock over a wide range of frequencies
US5250913A (en) * 1992-02-21 1993-10-05 Advanced Micro Devices, Inc. Variable pulse width phase detector
US5365130A (en) * 1992-08-07 1994-11-15 Vlsi Technology, Inc. Self-compensating output pad for an integrated circuit and method therefor

Also Published As

Publication number Publication date
SE9300624L (sv) 1994-08-25
BR9406373A (pt) 1996-01-16
EP0686319A1 (en) 1995-12-13
SE500929C2 (sv) 1994-10-03
AU6158794A (en) 1994-09-14
FI953953A (fi) 1995-08-23
KR960701512A (ko) 1996-02-24
NO953307L (no) 1995-10-19
JPH08506949A (ja) 1996-07-23
US5471165A (en) 1995-11-28
SE9300624D0 (sv) 1993-02-24
MXPA94001092A (es) 2004-08-20
NO953307D0 (no) 1995-08-23
AU676022B2 (en) 1997-02-27
CN1118205A (zh) 1996-03-06
CA2154252A1 (en) 1994-09-01
WO1994019868A1 (en) 1994-09-01

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