FI946158A - Digitaalisen integroidun piirin arkkitehtuuri - Google Patents

Digitaalisen integroidun piirin arkkitehtuuri Download PDF

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Publication number
FI946158A
FI946158A FI946158A FI946158A FI946158A FI 946158 A FI946158 A FI 946158A FI 946158 A FI946158 A FI 946158A FI 946158 A FI946158 A FI 946158A FI 946158 A FI946158 A FI 946158A
Authority
FI
Finland
Prior art keywords
integrated circuit
circuit architecture
digital integrated
architecture
digital
Prior art date
Application number
FI946158A
Other languages
English (en)
Swedish (sv)
Other versions
FI946158A0 (fi
Inventor
Gomez Rafael Sanz
Gonzalez Jose Luis Merino
Saenz Fernando Ortiz
Serratosa Maria Del Gutierrez
Original Assignee
Alcatel Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Nv filed Critical Alcatel Nv
Publication of FI946158A0 publication Critical patent/FI946158A0/fi
Publication of FI946158A publication Critical patent/FI946158A/fi

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
FI946158A 1993-12-30 1994-12-29 Digitaalisen integroidun piirin arkkitehtuuri FI946158A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9302723A ES2078173B1 (es) 1993-12-30 1993-12-30 Arquitectura de circuitos integrados digitales.

Publications (2)

Publication Number Publication Date
FI946158A0 FI946158A0 (fi) 1994-12-29
FI946158A true FI946158A (fi) 1995-07-01

Family

ID=8284071

Family Applications (1)

Application Number Title Priority Date Filing Date
FI946158A FI946158A (fi) 1993-12-30 1994-12-29 Digitaalisen integroidun piirin arkkitehtuuri

Country Status (6)

Country Link
EP (1) EP0661808A3 (fi)
JP (1) JPH0823265A (fi)
AU (1) AU8029994A (fi)
CA (1) CA2139283A1 (fi)
ES (1) ES2078173B1 (fi)
FI (1) FI946158A (fi)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6035400A (ja) * 1983-08-05 1985-02-23 Sharp Corp 相補形金属酸化膜半導体を用いた送信装置
US5025419A (en) * 1988-03-31 1991-06-18 Sony Corporation Input/output circuit
US4856035A (en) * 1988-05-26 1989-08-08 Raytheon Company CMOS binary up/down counter
JPH0815252B2 (ja) * 1991-03-27 1996-02-14 松下電器産業株式会社 フリップフロップ回路
JPH05199080A (ja) * 1992-01-17 1993-08-06 Sony Corp 相補型論理回路

Also Published As

Publication number Publication date
CA2139283A1 (en) 1995-07-01
ES2078173R (fi) 1997-05-16
EP0661808A2 (en) 1995-07-05
EP0661808A3 (en) 1996-05-22
AU8029994A (en) 1995-07-06
ES2078173A2 (es) 1995-12-01
JPH0823265A (ja) 1996-01-23
ES2078173B1 (es) 1998-01-16
FI946158A0 (fi) 1994-12-29

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Legal Events

Date Code Title Description
FD Application lapsed