FI89432B - Genering av en klockfrekvens i ett smart card graenssnitt - Google Patents

Genering av en klockfrekvens i ett smart card graenssnitt Download PDF

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Publication number
FI89432B
FI89432B FI913108A FI913108A FI89432B FI 89432 B FI89432 B FI 89432B FI 913108 A FI913108 A FI 913108A FI 913108 A FI913108 A FI 913108A FI 89432 B FI89432 B FI 89432B
Authority
FI
Finland
Prior art keywords
clock frequency
smart card
circuit
uart
circuit arrangement
Prior art date
Application number
FI913108A
Other languages
English (en)
Finnish (fi)
Other versions
FI89432C (sv
FI913108A (fi
FI913108A0 (fi
Inventor
Rune Lindholm
Original Assignee
Nokia Mobile Phones Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Mobile Phones Ltd filed Critical Nokia Mobile Phones Ltd
Priority to FI913108A priority Critical patent/FI89432C/sv
Publication of FI913108A0 publication Critical patent/FI913108A0/fi
Priority to EP92305526A priority patent/EP0525963B1/en
Priority to DE69229820T priority patent/DE69229820T2/de
Priority to JP4169413A priority patent/JPH05227147A/ja
Publication of FI913108A publication Critical patent/FI913108A/fi
Application granted granted Critical
Publication of FI89432B publication Critical patent/FI89432B/fi
Publication of FI89432C publication Critical patent/FI89432C/sv
Priority to US08/288,976 priority patent/US5487084A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0008—General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Claims (5)

1. Kretsarrangemang for generering av en klockfrekvens i ett smartcard gränssnitt i och för mottagning och/eller sändning • av data, kännetecknat av att med hjälp av en fasläst slinga 5 (PLL) i kretsarrangemanget frän smartcardens klockfrekvens {f(IC)) härleds klockfrekvensen (f(UART)) för UART-kretsen tili smartcardens gränssnitt.
2. Kretsarrangemang enligt patentkravet 1, kännetecknat av att 10 det därtill innefattar programmerbara räknare (N1-N4), medelst vilka relationen mellan smartcardens klockf rekvens (f (IC)) och den av gränsnittet förmedlade datahastigheten (f(D)) genom en yttre styrning kan inställas pä pä förhand fastställda värden.
3. Kretsarrangemang enligt patentkravet 1 eller 2, känneteck nat av att klockfrekvensen (f(UART)) för UART-kretsen är 16 gänger datahastigheten (f(D)).
4. Kretsarrangemang enligt nägot av de föregäende patentkra-20 ven, kännetecknat av att koefficienterna för de programmerbara räknarna kan valjas sä, att förhällandet mellan smartcardens • . klockfrekvens (f(IC)) och den av gränsnittet förmedlade data hastigheten (f(D)) blir 372, 512, 744, 768, 1024, 1116 eller 1488. ' ‘25
5. Kretsarrangemang enligt nägot av de föregäende patentkraven 1-3, kännetecknat av att koefficienterna för de programmerbara räknarna kan väljas sä, att förhällandet mellan smartcardens klockfrekvens (f(IC)) och den av gränsnittet förmedlade data- :- :30 hastigheten (f(D)) blir 2n.
FI913108A 1991-06-26 1991-06-26 Genering av en klockfrekvens i ett smart card gränssnitt FI89432C (sv)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FI913108A FI89432C (sv) 1991-06-26 1991-06-26 Genering av en klockfrekvens i ett smart card gränssnitt
EP92305526A EP0525963B1 (en) 1991-06-26 1992-06-17 Generation of a clock frequency in a smart card interface
DE69229820T DE69229820T2 (de) 1991-06-26 1992-06-17 Taktfrequenzgeneration in einer Chipkartenschnittstelle
JP4169413A JPH05227147A (ja) 1991-06-26 1992-06-26 スマートカードインターフェースにおけるクロック周波数の生成回路
US08/288,976 US5487084A (en) 1991-06-26 1994-08-11 Generation of a clock frequency in a smart card interface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI913108 1991-06-26
FI913108A FI89432C (sv) 1991-06-26 1991-06-26 Genering av en klockfrekvens i ett smart card gränssnitt

Publications (4)

Publication Number Publication Date
FI913108A0 FI913108A0 (fi) 1991-06-26
FI913108A FI913108A (fi) 1992-12-27
FI89432B true FI89432B (fi) 1993-06-15
FI89432C FI89432C (sv) 1993-09-27

Family

ID=8532797

Family Applications (1)

Application Number Title Priority Date Filing Date
FI913108A FI89432C (sv) 1991-06-26 1991-06-26 Genering av en klockfrekvens i ett smart card gränssnitt

Country Status (5)

Country Link
US (1) US5487084A (sv)
EP (1) EP0525963B1 (sv)
JP (1) JPH05227147A (sv)
DE (1) DE69229820T2 (sv)
FI (1) FI89432C (sv)

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US5887250A (en) * 1996-07-12 1999-03-23 Nokia Mobile Phones Limited Mobile station having lock code based on secure value
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FI104223B1 (sv) * 1996-12-17 1999-11-30 Nokia Mobile Phones Ltd Förfarande för förmedling av ett SIM-korts styrkommandon från en extern apparat till ett SIM-kort
IL120213A (en) 1997-02-13 2000-08-13 Luzzatto Marco Method and apparatus for recording and reproducing computer pointer outputs and events
KR100237443B1 (ko) * 1997-02-26 2000-01-15 윤종용 디지털 셀룰라 무선 복합 단말기 및 그 단말기에서의 지역시각 표시방법
JPH11150608A (ja) * 1997-07-09 1999-06-02 Hisao Itou プリペイドカード式携帯電話機
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US6343364B1 (en) * 2000-07-13 2002-01-29 Schlumberger Malco Inc. Method and device for local clock generation using universal serial bus downstream received signals DP and DM
EP1646150B1 (de) 2002-12-23 2007-02-14 Infineon Technologies AG Verfahren und Vorrichtung zum Extrahieren einer einem Datenstrom zugrundeliegenden Taktfrequenz
DE10262079A1 (de) * 2002-12-23 2004-11-18 Infineon Technologies Ag Verfahren und Vorrichtung zum Extrahieren einer einem Datenstrom zugrundeliegenden Taktfrequenz
DE10260656B4 (de) * 2002-12-23 2006-03-30 Infineon Technologies Ag Verfahren und Vorrichtung zum Extrahieren einer einem Datenstrom zugrundeliegenden Taktfrequenz
US7339365B2 (en) * 2003-05-27 2008-03-04 Nxp B.V. Phase detector and method of phase detection
JP2006303794A (ja) * 2005-04-19 2006-11-02 Mitsubishi Electric Corp デジタル制御型位相合成回路システム
KR101506337B1 (ko) 2008-03-07 2015-03-26 삼성전자주식회사 스마트 카드 시스템 및 그 구동 방법
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Also Published As

Publication number Publication date
FI89432C (sv) 1993-09-27
US5487084A (en) 1996-01-23
FI913108A (fi) 1992-12-27
JPH05227147A (ja) 1993-09-03
EP0525963A2 (en) 1993-02-03
DE69229820T2 (de) 2000-01-27
DE69229820D1 (de) 1999-09-23
EP0525963B1 (en) 1999-08-18
EP0525963A3 (en) 1994-06-15
FI913108A0 (fi) 1991-06-26

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