FI873922A - Procedur foer inkorporering av tidsparametrar i synteser hos logikkretsplanering. - Google Patents

Procedur foer inkorporering av tidsparametrar i synteser hos logikkretsplanering. Download PDF

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Publication number
FI873922A
FI873922A FI873922A FI873922A FI873922A FI 873922 A FI873922 A FI 873922A FI 873922 A FI873922 A FI 873922A FI 873922 A FI873922 A FI 873922A FI 873922 A FI873922 A FI 873922A
Authority
FI
Finland
Prior art keywords
timing
circuit
location
signal
paths
Prior art date
Application number
FI873922A
Other languages
English (en)
Other versions
FI873922A0 (fi
Inventor
Donald F Hooper
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of FI873922A0 publication Critical patent/FI873922A0/fi
Publication of FI873922A publication Critical patent/FI873922A/fi

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
FI873922A 1986-09-12 1987-09-10 Procedur foer inkorporering av tidsparametrar i synteser hos logikkretsplanering. FI873922A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US90751486A 1986-09-12 1986-09-12

Publications (2)

Publication Number Publication Date
FI873922A0 FI873922A0 (fi) 1987-09-10
FI873922A true FI873922A (fi) 1988-03-13

Family

ID=25424232

Family Applications (1)

Application Number Title Priority Date Filing Date
FI873922A FI873922A (fi) 1986-09-12 1987-09-10 Procedur foer inkorporering av tidsparametrar i synteser hos logikkretsplanering.

Country Status (8)

Country Link
EP (1) EP0259705B1 (fi)
JP (1) JPS63155268A (fi)
AT (1) ATE112403T1 (fi)
AU (1) AU7728387A (fi)
DE (1) DE3750602T2 (fi)
DK (1) DK473587A (fi)
FI (1) FI873922A (fi)
IL (1) IL83618A (fi)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003487A (en) * 1988-06-28 1991-03-26 International Business Machines Corporation Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
US5210700A (en) * 1990-02-20 1993-05-11 International Business Machines Corporation Automatic delay adjustment for static timing analysis
DE10101540A1 (de) 2001-01-15 2002-08-01 Infineon Technologies Ag Verfahren zur Bestimmung des kritischen Pfades einer integrierten Schaltung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks

Also Published As

Publication number Publication date
DK473587D0 (da) 1987-09-11
DE3750602T2 (de) 1995-03-09
EP0259705A2 (en) 1988-03-16
DK473587A (da) 1988-03-13
ATE112403T1 (de) 1994-10-15
EP0259705B1 (en) 1994-09-28
DE3750602D1 (de) 1994-11-03
FI873922A0 (fi) 1987-09-10
JPS63155268A (ja) 1988-06-28
IL83618A0 (en) 1988-01-31
AU7728387A (en) 1988-03-17
IL83618A (en) 1991-08-16
EP0259705A3 (en) 1990-10-03

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Legal Events

Date Code Title Description
FD Application lapsed

Owner name: DIGITAL EQUIPMENT CORPORATION