ATE112403T1 - Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen. - Google Patents

Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen.

Info

Publication number
ATE112403T1
ATE112403T1 AT87112428T AT87112428T ATE112403T1 AT E112403 T1 ATE112403 T1 AT E112403T1 AT 87112428 T AT87112428 T AT 87112428T AT 87112428 T AT87112428 T AT 87112428T AT E112403 T1 ATE112403 T1 AT E112403T1
Authority
AT
Austria
Prior art keywords
timing
circuit
location
signal
paths
Prior art date
Application number
AT87112428T
Other languages
English (en)
Inventor
Donald F Hooper
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE112403T1 publication Critical patent/ATE112403T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Recording Measured Values (AREA)
  • Image Generation (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Stereophonic System (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Image Processing (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Peptides Or Proteins (AREA)
AT87112428T 1986-09-12 1987-08-26 Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen. ATE112403T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US90751486A 1986-09-12 1986-09-12

Publications (1)

Publication Number Publication Date
ATE112403T1 true ATE112403T1 (de) 1994-10-15

Family

ID=25424232

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87112428T ATE112403T1 (de) 1986-09-12 1987-08-26 Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen.

Country Status (8)

Country Link
EP (1) EP0259705B1 (de)
JP (1) JPS63155268A (de)
AT (1) ATE112403T1 (de)
AU (1) AU7728387A (de)
DE (1) DE3750602T2 (de)
DK (1) DK473587A (de)
FI (1) FI873922A7 (de)
IL (1) IL83618A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003487A (en) * 1988-06-28 1991-03-26 International Business Machines Corporation Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
US5210700A (en) * 1990-02-20 1993-05-11 International Business Machines Corporation Automatic delay adjustment for static timing analysis
DE10101540A1 (de) * 2001-01-15 2002-08-01 Infineon Technologies Ag Verfahren zur Bestimmung des kritischen Pfades einer integrierten Schaltung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks

Also Published As

Publication number Publication date
DK473587D0 (da) 1987-09-11
EP0259705A3 (en) 1990-10-03
EP0259705B1 (de) 1994-09-28
DK473587A (da) 1988-03-13
FI873922A7 (fi) 1988-03-13
JPS63155268A (ja) 1988-06-28
IL83618A0 (en) 1988-01-31
EP0259705A2 (de) 1988-03-16
FI873922A0 (fi) 1987-09-10
DE3750602D1 (de) 1994-11-03
IL83618A (en) 1991-08-16
DE3750602T2 (de) 1995-03-09
AU7728387A (en) 1988-03-17

Similar Documents

Publication Publication Date Title
DE69012492D1 (de) Methode zur Erzeugung von Qualitätsfaktoren für binäre Zahlen erhalten durch Viterbi-Analyse eines Signals.
ATE112403T1 (de) Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen.
GB1532418A (en) System for reading an optical recording of binary numerical data
DE69230520D1 (de) Verfahren und Anordung zur Erzeugung von Summeinformation-/Rundungskontrolle-Signal
EP0090047A1 (de) System zur kodierung und entkodierung binärer daten
MY105219A (en) Signal processing apparatus and method
DE3882114D1 (de) Verfahren zur uebertragung eines digitalsignals.
DE3575648D1 (de) Verfahren zur magnetischen aufzeichnung und wiedergabe von telekommunikations-signalen, insbesondere von videotext- und/oder kabeltext-signalen.
US7720663B1 (en) Delay analysis system
KR850001100B1 (ko) 잡음 제거회로
SU875375A1 (ru) Устройство дл ввода информации
JPS5788599A (en) Data access device
JPS5785124A (en) Clock distributing system
JPS5798111A (en) Magnetic recording system of digital signal
JPS55153183A (en) Magnetic recording system
JPS605492A (ja) 半導体メモリ装置のアドレスバツフア回路
SU698042A1 (ru) Система воспроизведени данных
SU1471309A2 (ru) Управл емый делитель частоты
SU1081654A1 (ru) Устройство дл воспроизведени цифровой информации с магнитного носител
SU583438A1 (ru) Ячейка однородной трассирующей среды
JPS5685127A (en) Digital signal processor
JPS5745754A (en) Clock pickup circuit for dmi code train
JPS5750308A (en) Time base correcting device
JPS57106229A (en) Cmos multiinput storage circuit
JPS63254823A (ja) Ｄ形フリップフロップを使用した分周回路

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties