ATE112403T1 - Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen. - Google Patents

Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen.

Info

Publication number
ATE112403T1
ATE112403T1 AT87112428T AT87112428T ATE112403T1 AT E112403 T1 ATE112403 T1 AT E112403T1 AT 87112428 T AT87112428 T AT 87112428T AT 87112428 T AT87112428 T AT 87112428T AT E112403 T1 ATE112403 T1 AT E112403T1
Authority
AT
Austria
Prior art keywords
timing
circuit
location
signal
paths
Prior art date
Application number
AT87112428T
Other languages
English (en)
Inventor
Donald F Hooper
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE112403T1 publication Critical patent/ATE112403T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Peptides Or Proteins (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Image Generation (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Stereophonic System (AREA)
  • Recording Measured Values (AREA)
  • Image Processing (AREA)
AT87112428T 1986-09-12 1987-08-26 Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen. ATE112403T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US90751486A 1986-09-12 1986-09-12

Publications (1)

Publication Number Publication Date
ATE112403T1 true ATE112403T1 (de) 1994-10-15

Family

ID=25424232

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87112428T ATE112403T1 (de) 1986-09-12 1987-08-26 Verfahren zur aufnahme von zeitparametern in der synthesis von logischen schaltungsentwürfen.

Country Status (8)

Country Link
EP (1) EP0259705B1 (de)
JP (1) JPS63155268A (de)
AT (1) ATE112403T1 (de)
AU (1) AU7728387A (de)
DE (1) DE3750602T2 (de)
DK (1) DK473587A (de)
FI (1) FI873922A (de)
IL (1) IL83618A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003487A (en) * 1988-06-28 1991-03-26 International Business Machines Corporation Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
US5210700A (en) * 1990-02-20 1993-05-11 International Business Machines Corporation Automatic delay adjustment for static timing analysis
DE10101540A1 (de) * 2001-01-15 2002-08-01 Infineon Technologies Ag Verfahren zur Bestimmung des kritischen Pfades einer integrierten Schaltung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks

Also Published As

Publication number Publication date
FI873922A (fi) 1988-03-13
IL83618A0 (en) 1988-01-31
DE3750602T2 (de) 1995-03-09
JPS63155268A (ja) 1988-06-28
FI873922A0 (fi) 1987-09-10
IL83618A (en) 1991-08-16
DK473587D0 (da) 1987-09-11
DK473587A (da) 1988-03-13
DE3750602D1 (de) 1994-11-03
EP0259705B1 (de) 1994-09-28
EP0259705A2 (de) 1988-03-16
AU7728387A (en) 1988-03-17
EP0259705A3 (en) 1990-10-03

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties